android_kernel_xiaomi_sm8350/arch/xtensa/mm
Chris Zankel 0b2c3afdaa [XTENSA] Fix icache flush for cache aliasing
Set the execution bit in the temporary TLB when we flush the
instruction cache.

Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13 17:08:18 -08:00
..
cache.c [XTENSA] Flush the page-address in update-mmu instead of user-address 2008-02-13 16:58:51 -08:00
fault.c
init.c [XTENSA] Fix argument list for pgd_ctor constructor. 2008-02-13 16:54:12 -08:00
Makefile
misc.S [XTENSA] Fix icache flush for cache aliasing 2008-02-13 17:08:18 -08:00
pgtable.c
tlb.c