82a96f5790
This patch adds drivers for IXP4xx hardware Queue Manager and for Network Processor Engines. Requires patch #4712 (reading/writing CPU feature (aka fuse) bits). Posted to linux-arm-kernel on 2 Dec 2007 and revised. Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
/*
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* Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*/
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#ifndef IXP4XX_QMGR_H
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#define IXP4XX_QMGR_H
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#include <linux/io.h>
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#include <linux/kernel.h>
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#define HALF_QUEUES 32
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#define QUEUES 64 /* only 32 lower queues currently supported */
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#define MAX_QUEUE_LENGTH 4 /* in dwords */
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#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
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#define QUEUE_STAT1_NEARLY_EMPTY 2
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#define QUEUE_STAT1_NEARLY_FULL 4
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#define QUEUE_STAT1_FULL 8
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#define QUEUE_STAT2_UNDERFLOW 1
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#define QUEUE_STAT2_OVERFLOW 2
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#define QUEUE_WATERMARK_0_ENTRIES 0
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#define QUEUE_WATERMARK_1_ENTRY 1
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#define QUEUE_WATERMARK_2_ENTRIES 2
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#define QUEUE_WATERMARK_4_ENTRIES 3
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#define QUEUE_WATERMARK_8_ENTRIES 4
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#define QUEUE_WATERMARK_16_ENTRIES 5
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#define QUEUE_WATERMARK_32_ENTRIES 6
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#define QUEUE_WATERMARK_64_ENTRIES 7
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/* queue interrupt request conditions */
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#define QUEUE_IRQ_SRC_EMPTY 0
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#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
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#define QUEUE_IRQ_SRC_NEARLY_FULL 2
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#define QUEUE_IRQ_SRC_FULL 3
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#define QUEUE_IRQ_SRC_NOT_EMPTY 4
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#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
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#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
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#define QUEUE_IRQ_SRC_NOT_FULL 7
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struct qmgr_regs {
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u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
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u32 stat1[4]; /* 0x400 - 0x40F */
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u32 stat2[2]; /* 0x410 - 0x417 */
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u32 statne_h; /* 0x418 - queue nearly empty */
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u32 statf_h; /* 0x41C - queue full */
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u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
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u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
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u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
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u32 reserved[1776];
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u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
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};
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void qmgr_set_irq(unsigned int queue, int src,
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void (*handler)(void *pdev), void *pdev);
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void qmgr_enable_irq(unsigned int queue);
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void qmgr_disable_irq(unsigned int queue);
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/* request_ and release_queue() must be called from non-IRQ context */
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int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
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unsigned int nearly_empty_watermark,
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unsigned int nearly_full_watermark);
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void qmgr_release_queue(unsigned int queue);
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static inline void qmgr_put_entry(unsigned int queue, u32 val)
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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__raw_writel(val, &qmgr_regs->acc[queue][0]);
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}
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static inline u32 qmgr_get_entry(unsigned int queue)
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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return __raw_readl(&qmgr_regs->acc[queue][0]);
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}
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static inline int qmgr_get_stat1(unsigned int queue)
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
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>> ((queue & 7) << 2)) & 0xF;
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}
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static inline int qmgr_get_stat2(unsigned int queue)
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
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>> ((queue & 0xF) << 1)) & 0x3;
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}
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static inline int qmgr_stat_empty(unsigned int queue)
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{
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return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
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}
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static inline int qmgr_stat_nearly_empty(unsigned int queue)
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{
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return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
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}
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static inline int qmgr_stat_nearly_full(unsigned int queue)
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{
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return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
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}
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static inline int qmgr_stat_full(unsigned int queue)
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{
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return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
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}
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static inline int qmgr_stat_underflow(unsigned int queue)
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{
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return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
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}
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static inline int qmgr_stat_overflow(unsigned int queue)
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{
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return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
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}
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#endif
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