11c1965687
There are a lot of bogus cpu_data-> references that only end up working for the boot CPU, convert these to current_cpu_data to fixup SMP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
/*
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* debugfs ops for the L1 cache
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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enum cache_type {
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CACHE_TYPE_ICACHE,
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CACHE_TYPE_DCACHE,
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CACHE_TYPE_UNIFIED,
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};
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static int cache_seq_show(struct seq_file *file, void *iter)
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{
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unsigned int cache_type = (unsigned int)file->private;
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struct cache_info *cache;
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unsigned int waysize, way, cache_size;
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unsigned long ccr, base;
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static unsigned long addrstart = 0;
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/*
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* Go uncached immediately so we don't skew the results any
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* more than we already are..
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*/
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jump_to_P2();
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ccr = ctrl_inl(CCR);
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if ((ccr & CCR_CACHE_ENABLE) == 0) {
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back_to_P1();
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seq_printf(file, "disabled\n");
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return 0;
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}
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if (cache_type == CACHE_TYPE_DCACHE) {
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base = CACHE_OC_ADDRESS_ARRAY;
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cache = ¤t_cpu_data.dcache;
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} else {
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base = CACHE_IC_ADDRESS_ARRAY;
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cache = ¤t_cpu_data.icache;
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}
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/*
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* Due to the amount of data written out (depending on the cache size),
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* we may be iterated over multiple times. In this case, keep track of
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* the entry position in addrstart, and rewind it when we've hit the
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* end of the cache.
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*
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* Likewise, the same code is used for multiple caches, so care must
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* be taken for bouncing addrstart back and forth so the appropriate
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* cache is hit.
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*/
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cache_size = cache->ways * cache->sets * cache->linesz;
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if (((addrstart & 0xff000000) != base) ||
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(addrstart & 0x00ffffff) > cache_size)
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addrstart = base;
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waysize = cache->sets;
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/*
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* If the OC is already in RAM mode, we only have
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* half of the entries to consider..
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*/
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if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE)
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waysize >>= 1;
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waysize <<= cache->entry_shift;
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for (way = 0; way < cache->ways; way++) {
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unsigned long addr;
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unsigned int line;
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seq_printf(file, "-----------------------------------------\n");
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seq_printf(file, "Way %d\n", way);
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seq_printf(file, "-----------------------------------------\n");
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for (addr = addrstart, line = 0;
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addr < addrstart + waysize;
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addr += cache->linesz, line++) {
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unsigned long data = ctrl_inl(addr);
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/* Check the V bit, ignore invalid cachelines */
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if ((data & 1) == 0)
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continue;
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/* U: Dirty, cache tag is 10 bits up */
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seq_printf(file, "%3d: %c 0x%lx\n",
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line, data & 2 ? 'U' : ' ',
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data & 0x1ffffc00);
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}
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addrstart += cache->way_incr;
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}
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back_to_P1();
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return 0;
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}
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static int cache_debugfs_open(struct inode *inode, struct file *file)
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{
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return single_open(file, cache_seq_show, inode->i_private);
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}
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static const struct file_operations cache_debugfs_fops = {
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.owner = THIS_MODULE,
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.open = cache_debugfs_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = seq_release,
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};
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static int __init cache_debugfs_init(void)
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{
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struct dentry *dcache_dentry, *icache_dentry;
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dcache_dentry = debugfs_create_file("dcache", S_IRUSR, NULL,
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(unsigned int *)CACHE_TYPE_DCACHE,
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&cache_debugfs_fops);
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if (IS_ERR(dcache_dentry))
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return PTR_ERR(dcache_dentry);
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icache_dentry = debugfs_create_file("icache", S_IRUSR, NULL,
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(unsigned int *)CACHE_TYPE_ICACHE,
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&cache_debugfs_fops);
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if (IS_ERR(icache_dentry)) {
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debugfs_remove(dcache_dentry);
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return PTR_ERR(icache_dentry);
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}
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return 0;
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}
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module_init(cache_debugfs_init);
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MODULE_LICENSE("GPL v2");
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