312 lines
8.1 KiB
C
312 lines
8.1 KiB
C
/*
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* linux/arch/arm/mach-imx/irq.c
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
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* Copied from the motorola bsp package and added gpio demux
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* interrupt handler
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*/
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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/*
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*
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* We simply use the ENABLE DISABLE registers inside of the IMX
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* to turn on/off specific interrupts.
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*
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*/
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#define INTCNTL_OFF 0x00
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#define NIMASK_OFF 0x04
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#define INTENNUM_OFF 0x08
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#define INTDISNUM_OFF 0x0C
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#define INTENABLEH_OFF 0x10
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#define INTENABLEL_OFF 0x14
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#define INTTYPEH_OFF 0x18
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#define INTTYPEL_OFF 0x1C
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#define NIPRIORITY_OFF(x) (0x20+4*(7-(x)))
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#define NIVECSR_OFF 0x40
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#define FIVECSR_OFF 0x44
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#define INTSRCH_OFF 0x48
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#define INTSRCL_OFF 0x4C
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#define INTFRCH_OFF 0x50
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#define INTFRCL_OFF 0x54
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#define NIPNDH_OFF 0x58
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#define NIPNDL_OFF 0x5C
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#define FIPNDH_OFF 0x60
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#define FIPNDL_OFF 0x64
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#define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE)
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#define IMX_AITC_INTCNTL (VA_AITC_BASE + INTCNTL_OFF)
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#define IMX_AITC_NIMASK (VA_AITC_BASE + NIMASK_OFF)
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#define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF)
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#define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF)
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#define IMX_AITC_INTENABLEH (VA_AITC_BASE + INTENABLEH_OFF)
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#define IMX_AITC_INTENABLEL (VA_AITC_BASE + INTENABLEL_OFF)
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#define IMX_AITC_INTTYPEH (VA_AITC_BASE + INTTYPEH_OFF)
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#define IMX_AITC_INTTYPEL (VA_AITC_BASE + INTTYPEL_OFF)
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#define IMX_AITC_NIPRIORITY(x) (VA_AITC_BASE + NIPRIORITY_OFF(x))
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#define IMX_AITC_NIVECSR (VA_AITC_BASE + NIVECSR_OFF)
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#define IMX_AITC_FIVECSR (VA_AITC_BASE + FIVECSR_OFF)
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#define IMX_AITC_INTSRCH (VA_AITC_BASE + INTSRCH_OFF)
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#define IMX_AITC_INTSRCL (VA_AITC_BASE + INTSRCL_OFF)
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#define IMX_AITC_INTFRCH (VA_AITC_BASE + INTFRCH_OFF)
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#define IMX_AITC_INTFRCL (VA_AITC_BASE + INTFRCL_OFF)
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#define IMX_AITC_NIPNDH (VA_AITC_BASE + NIPNDH_OFF)
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#define IMX_AITC_NIPNDL (VA_AITC_BASE + NIPNDL_OFF)
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#define IMX_AITC_FIPNDH (VA_AITC_BASE + FIPNDH_OFF)
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#define IMX_AITC_FIPNDL (VA_AITC_BASE + FIPNDL_OFF)
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#if 0
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#define DEBUG_IRQ(fmt...) printk(fmt)
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#else
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#define DEBUG_IRQ(fmt...) do { } while (0)
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#endif
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static void
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imx_mask_irq(unsigned int irq)
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{
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__raw_writel(irq, IMX_AITC_INTDISNUM);
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}
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static void
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imx_unmask_irq(unsigned int irq)
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{
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__raw_writel(irq, IMX_AITC_INTENNUM);
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}
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#ifdef CONFIG_FIQ
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int imx_set_irq_fiq(unsigned int irq, unsigned int type)
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{
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unsigned int irqt;
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if (irq >= IMX_IRQS)
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return -EINVAL;
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if (irq < IMX_IRQS / 2) {
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irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq);
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__raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL);
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} else {
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irq -= IMX_IRQS / 2;
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irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq);
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__raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH);
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}
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return 0;
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}
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EXPORT_SYMBOL(imx_set_irq_fiq);
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#endif /* CONFIG_FIQ */
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static int
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imx_gpio_irq_type(unsigned int _irq, unsigned int type)
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{
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unsigned int irq_type = 0, irq, reg, bit;
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irq = _irq - IRQ_GPIOA(0);
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reg = irq >> 5;
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bit = 1 << (irq % 32);
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if (type == IRQ_TYPE_PROBE) {
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/* Don't mess with enabled GPIOs using preconfigured edges or
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GPIOs set to alternate function during probe */
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/* TODO: support probe */
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// if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
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// GPIO_bit(gpio))
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// return 0;
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// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
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// return 0;
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// type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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GIUS(reg) |= bit;
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DDIR(reg) &= ~(bit);
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DEBUG_IRQ("setting type of irq %d to ", _irq);
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if (type & IRQ_TYPE_EDGE_RISING) {
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DEBUG_IRQ("rising edges\n");
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irq_type = 0x0;
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}
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if (type & IRQ_TYPE_EDGE_FALLING) {
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DEBUG_IRQ("falling edges\n");
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irq_type = 0x1;
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}
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if (type & IRQ_TYPE_LEVEL_LOW) {
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DEBUG_IRQ("low level\n");
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irq_type = 0x3;
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}
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if (type & IRQ_TYPE_LEVEL_HIGH) {
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DEBUG_IRQ("high level\n");
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irq_type = 0x2;
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}
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if (irq % 32 < 16) {
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ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
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(irq_type << ((irq % 16) * 2));
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} else {
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ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
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(irq_type << ((irq % 16) * 2));
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}
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return 0;
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}
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static void
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imx_gpio_ack_irq(unsigned int irq)
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{
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DEBUG_IRQ("%s: irq %d\n", __func__, irq);
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ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
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}
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static void
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imx_gpio_mask_irq(unsigned int irq)
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{
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DEBUG_IRQ("%s: irq %d\n", __func__, irq);
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IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
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}
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static void
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imx_gpio_unmask_irq(unsigned int irq)
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{
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DEBUG_IRQ("%s: irq %d\n", __func__, irq);
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IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
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}
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static void
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imx_gpio_handler(unsigned int mask, unsigned int irq,
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struct irq_desc *desc)
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{
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while (mask) {
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if (mask & 1) {
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DEBUG_IRQ("handling irq %d\n", irq);
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generic_handle_irq(irq);
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}
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irq++;
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mask >>= 1;
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}
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}
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static void
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imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = ISR(0);
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irq = IRQ_GPIOA(0);
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imx_gpio_handler(mask, irq, desc);
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}
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static void
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imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = ISR(1);
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irq = IRQ_GPIOB(0);
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imx_gpio_handler(mask, irq, desc);
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}
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static void
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imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = ISR(2);
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irq = IRQ_GPIOC(0);
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imx_gpio_handler(mask, irq, desc);
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}
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static void
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imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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unsigned int mask, irq;
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mask = ISR(3);
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irq = IRQ_GPIOD(0);
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imx_gpio_handler(mask, irq, desc);
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}
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static struct irq_chip imx_internal_chip = {
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.name = "MPU",
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.ack = imx_mask_irq,
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.mask = imx_mask_irq,
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.unmask = imx_unmask_irq,
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};
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static struct irq_chip imx_gpio_chip = {
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.name = "GPIO",
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.ack = imx_gpio_ack_irq,
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.mask = imx_gpio_mask_irq,
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.unmask = imx_gpio_unmask_irq,
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.set_type = imx_gpio_irq_type,
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};
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void __init
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imx_init_irq(void)
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{
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unsigned int irq;
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DEBUG_IRQ("Initializing imx interrupts\n");
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/* Disable all interrupts initially. */
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/* Do not rely on the bootloader. */
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__raw_writel(0, IMX_AITC_INTENABLEH);
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__raw_writel(0, IMX_AITC_INTENABLEL);
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/* Mask all GPIO interrupts as well */
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IMR(0) = 0;
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IMR(1) = 0;
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IMR(2) = 0;
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IMR(3) = 0;
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for (irq = 0; irq < IMX_IRQS; irq++) {
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set_irq_chip(irq, &imx_internal_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
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set_irq_chip(irq, &imx_gpio_chip);
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set_irq_handler(irq, handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
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set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
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set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
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set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
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/* Release masking of interrupts according to priority */
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__raw_writel(-1, IMX_AITC_NIMASK);
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#ifdef CONFIG_FIQ
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/* Initialize FIQ */
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init_FIQ();
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#endif
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}
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