3d0a3cc9d7
o Pause traffic during mac addr change. o Enable setting mac address for NX3031. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
551 lines
14 KiB
C
551 lines
14 KiB
C
/*
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* Copyright (C) 2003 - 2009 NetXen, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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* MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.
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*
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* Contact Information:
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* info@netxen.com
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* NetXen Inc,
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* 18922 Forge Drive
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* Cupertino, CA 95014-0701
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*
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*/
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#include "netxen_nic.h"
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#define NETXEN_GB_MAC_SOFT_RESET 0x80000000
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#define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
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#define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
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#define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
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static long phy_lock_timeout = 100000000;
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static int phy_lock(struct netxen_adapter *adapter)
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{
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int i;
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int done = 0, timeout = 0;
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while (!done) {
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done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
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if (done == 1)
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break;
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if (timeout >= phy_lock_timeout) {
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return -1;
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}
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timeout++;
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if (!in_atomic())
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schedule();
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else {
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for (i = 0; i < 20; i++)
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cpu_relax();
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}
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}
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NXWR32(adapter, NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
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return 0;
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}
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static int phy_unlock(struct netxen_adapter *adapter)
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{
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adapter->pci_read_immediate(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK));
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return 0;
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}
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/*
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* netxen_niu_gbe_phy_read - read a register from the GbE PHY via
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* mii management interface.
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*
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* Note: The MII management interface goes through port 0.
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* Individual phys are addressed as follows:
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* @param phy [15:8] phy id
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* @param reg [7:0] register number
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*
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* @returns 0 on success
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* -1 on error
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*
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*/
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int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
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__u32 * readval)
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{
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long timeout = 0;
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long result = 0;
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long restore = 0;
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long phy = adapter->physical_port;
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__u32 address;
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__u32 command;
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__u32 status;
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__u32 mac_cfg0;
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if (phy_lock(adapter) != 0) {
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return -1;
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}
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/*
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* MII mgmt all goes through port 0 MAC interface,
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* so it cannot be in reset
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*/
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mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
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if (netxen_gb_get_soft_reset(mac_cfg0)) {
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__u32 temp;
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temp = 0;
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netxen_gb_tx_reset_pb(temp);
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netxen_gb_rx_reset_pb(temp);
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netxen_gb_tx_reset_mac(temp);
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netxen_gb_rx_reset_mac(temp);
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
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return -EIO;
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restore = 1;
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}
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address = 0;
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netxen_gb_mii_mgmt_reg_addr(address, reg);
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netxen_gb_mii_mgmt_phy_addr(address, phy);
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
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return -EIO;
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command = 0; /* turn off any prior activity */
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
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return -EIO;
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/* send read command */
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netxen_gb_mii_mgmt_set_read_cycle(command);
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
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return -EIO;
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status = 0;
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do {
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status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
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timeout++;
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} while ((netxen_get_gb_mii_mgmt_busy(status)
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|| netxen_get_gb_mii_mgmt_notvalid(status))
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&& (timeout++ < NETXEN_NIU_PHY_WAITMAX));
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if (timeout < NETXEN_NIU_PHY_WAITMAX) {
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*readval = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_STATUS(0));
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result = 0;
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} else
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result = -1;
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if (restore)
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
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return -EIO;
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phy_unlock(adapter);
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return result;
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}
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/*
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* netxen_niu_gbe_phy_write - write a register to the GbE PHY via
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* mii management interface.
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*
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* Note: The MII management interface goes through port 0.
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* Individual phys are addressed as follows:
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* @param phy [15:8] phy id
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* @param reg [7:0] register number
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*
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* @returns 0 on success
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* -1 on error
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*
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*/
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int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
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__u32 val)
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{
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long timeout = 0;
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long result = 0;
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long restore = 0;
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long phy = adapter->physical_port;
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__u32 address;
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__u32 command;
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__u32 status;
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__u32 mac_cfg0;
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/*
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* MII mgmt all goes through port 0 MAC interface, so it
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* cannot be in reset
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*/
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mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
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if (netxen_gb_get_soft_reset(mac_cfg0)) {
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__u32 temp;
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temp = 0;
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netxen_gb_tx_reset_pb(temp);
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netxen_gb_rx_reset_pb(temp);
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netxen_gb_tx_reset_mac(temp);
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netxen_gb_rx_reset_mac(temp);
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
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return -EIO;
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restore = 1;
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}
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command = 0; /* turn off any prior activity */
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
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return -EIO;
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address = 0;
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netxen_gb_mii_mgmt_reg_addr(address, reg);
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netxen_gb_mii_mgmt_phy_addr(address, phy);
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
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return -EIO;
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), val))
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return -EIO;
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status = 0;
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do {
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status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
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timeout++;
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} while ((netxen_get_gb_mii_mgmt_busy(status))
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&& (timeout++ < NETXEN_NIU_PHY_WAITMAX));
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if (timeout < NETXEN_NIU_PHY_WAITMAX)
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result = 0;
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else
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result = -EIO;
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/* restore the state of port 0 MAC in case we tampered with it */
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if (restore)
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
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return -EIO;
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return result;
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}
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int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter)
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{
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NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x3f);
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return 0;
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}
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int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter)
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{
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int result = 0;
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__u32 enable = 0;
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netxen_set_phy_int_link_status_changed(enable);
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netxen_set_phy_int_autoneg_completed(enable);
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netxen_set_phy_int_speed_changed(enable);
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if (0 !=
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netxen_niu_gbe_phy_write(adapter,
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NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
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enable))
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result = -EIO;
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return result;
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}
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int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter)
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{
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NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x7f);
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return 0;
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}
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int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter)
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{
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int result = 0;
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if (0 !=
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netxen_niu_gbe_phy_write(adapter,
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NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
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result = -EIO;
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return result;
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}
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static int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter)
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{
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int result = 0;
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if (0 !=
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netxen_niu_gbe_phy_write(adapter,
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NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
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-EIO))
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result = -EIO;
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return result;
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}
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/*
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* netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
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*
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*/
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static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
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int port, long enable)
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{
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NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf1ff);
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NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
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NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
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NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
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NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
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if (enable) {
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/*
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* Do NOT enable flow control until a suitable solution for
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* shutting down pause frames is found.
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*/
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
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}
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if (netxen_niu_gbe_enable_phy_interrupts(adapter))
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printk(KERN_ERR "ERROR enabling PHY interrupts\n");
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if (netxen_niu_gbe_clear_phy_interrupts(adapter))
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printk(KERN_ERR "ERROR clearing PHY interrupts\n");
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}
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/*
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* netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
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*/
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static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
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int port, long enable)
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{
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NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf2ff);
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NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
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NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
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NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
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NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
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if (enable) {
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/*
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* Do NOT enable flow control until a suitable solution for
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* shutting down pause frames is found.
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*/
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
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}
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if (netxen_niu_gbe_enable_phy_interrupts(adapter))
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printk(KERN_ERR "ERROR enabling PHY interrupts\n");
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if (netxen_niu_gbe_clear_phy_interrupts(adapter))
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printk(KERN_ERR "ERROR clearing PHY interrupts\n");
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}
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int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
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{
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int result = 0;
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__u32 status;
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if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
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return 0;
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if (adapter->disable_phy_interrupts)
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adapter->disable_phy_interrupts(adapter);
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mdelay(2);
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if (0 == netxen_niu_gbe_phy_read(adapter,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, &status)) {
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if (netxen_get_phy_link(status)) {
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if (netxen_get_phy_speed(status) == 2) {
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netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
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} else if ((netxen_get_phy_speed(status) == 1)
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|| (netxen_get_phy_speed(status) == 0)) {
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netxen_niu_gbe_set_mii_mode(adapter, port, 1);
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} else {
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result = -1;
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}
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} else {
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/*
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* We don't have link. Cable must be unconnected.
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* Enable phy interrupts so we take action when
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* plugged in.
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*/
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
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NETXEN_GB_MAC_SOFT_RESET);
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NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
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NETXEN_GB_MAC_RESET_PROT_BLK |
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NETXEN_GB_MAC_ENABLE_TX_RX |
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NETXEN_GB_MAC_PAUSED_FRMS);
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if (netxen_niu_gbe_clear_phy_interrupts(adapter))
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printk(KERN_ERR
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"ERROR clearing PHY interrupts\n");
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if (netxen_niu_gbe_enable_phy_interrupts(adapter))
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printk(KERN_ERR
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"ERROR enabling PHY interrupts\n");
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if (netxen_niu_gbe_clear_phy_interrupts(adapter))
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printk(KERN_ERR
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"ERROR clearing PHY interrupts\n");
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result = -1;
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}
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} else {
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result = -EIO;
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}
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return result;
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}
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int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
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{
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if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
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NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
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NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
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}
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return 0;
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}
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/* Disable a GbE interface */
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int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
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{
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__u32 mac_cfg0;
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u32 port = adapter->physical_port;
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if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
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return 0;
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if (port > NETXEN_NIU_MAX_GBE_PORTS)
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return -EINVAL;
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mac_cfg0 = 0;
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netxen_gb_soft_reset(mac_cfg0);
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), mac_cfg0))
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return -EIO;
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return 0;
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}
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/* Disable an XG interface */
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int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
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{
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__u32 mac_cfg;
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u32 port = adapter->physical_port;
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if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
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return 0;
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if (port > NETXEN_NIU_MAX_XG_PORTS)
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return -EINVAL;
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mac_cfg = 0;
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if (NXWR32(adapter,
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NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
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return -EIO;
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return 0;
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}
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/* Set promiscuous mode for a GbE interface */
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int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
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u32 mode)
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{
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__u32 reg;
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u32 port = adapter->physical_port;
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if (port > NETXEN_NIU_MAX_GBE_PORTS)
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return -EINVAL;
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/* save previous contents */
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reg = NXRD32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR);
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if (mode == NETXEN_NIU_PROMISC_MODE) {
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switch (port) {
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case 0:
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netxen_clear_gb_drop_gb0(reg);
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break;
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case 1:
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netxen_clear_gb_drop_gb1(reg);
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break;
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case 2:
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netxen_clear_gb_drop_gb2(reg);
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break;
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case 3:
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netxen_clear_gb_drop_gb3(reg);
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break;
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default:
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return -EIO;
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}
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} else {
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switch (port) {
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case 0:
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netxen_set_gb_drop_gb0(reg);
|
|
break;
|
|
case 1:
|
|
netxen_set_gb_drop_gb1(reg);
|
|
break;
|
|
case 2:
|
|
netxen_set_gb_drop_gb2(reg);
|
|
break;
|
|
case 3:
|
|
netxen_set_gb_drop_gb3(reg);
|
|
break;
|
|
default:
|
|
return -EIO;
|
|
}
|
|
}
|
|
if (NXWR32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, reg))
|
|
return -EIO;
|
|
return 0;
|
|
}
|
|
|
|
int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
|
|
u32 mode)
|
|
{
|
|
__u32 reg;
|
|
u32 port = adapter->physical_port;
|
|
|
|
if (port > NETXEN_NIU_MAX_XG_PORTS)
|
|
return -EINVAL;
|
|
|
|
reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
|
|
if (mode == NETXEN_NIU_PROMISC_MODE)
|
|
reg = (reg | 0x2000UL);
|
|
else
|
|
reg = (reg & ~0x2000UL);
|
|
|
|
if (mode == NETXEN_NIU_ALLMULTI_MODE)
|
|
reg = (reg | 0x1000UL);
|
|
else
|
|
reg = (reg & ~0x1000UL);
|
|
|
|
NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
|
|
{
|
|
u32 mac_hi, mac_lo;
|
|
u32 reg_hi, reg_lo;
|
|
|
|
u8 phy = adapter->physical_port;
|
|
u8 phy_count = (adapter->ahw.port_type == NETXEN_NIC_XGBE) ?
|
|
NETXEN_NIU_MAX_XG_PORTS : NETXEN_NIU_MAX_GBE_PORTS;
|
|
|
|
if (phy >= phy_count)
|
|
return -EINVAL;
|
|
|
|
mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
|
|
mac_hi = addr[2] | ((u32)addr[3] << 8) |
|
|
((u32)addr[4] << 16) | ((u32)addr[5] << 24);
|
|
|
|
if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
|
|
reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
|
|
reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
|
|
} else {
|
|
reg_lo = NETXEN_NIU_GB_STATION_ADDR_1(phy);
|
|
reg_hi = NETXEN_NIU_GB_STATION_ADDR_0(phy);
|
|
}
|
|
|
|
/* write twice to flush */
|
|
if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
|
|
return -EIO;
|
|
if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|