d8678b5870
Add a common header file for working with the flattened device tree data structure and merge the shared data tags used by Microblaze and PowerPC Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au>
266 lines
7.4 KiB
ArmAsm
266 lines
7.4 KiB
ArmAsm
/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* MMU code derived from arch/ppc/kernel/head_4xx.S:
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* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
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* Initial PowerPC version.
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* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Rewritten for PReP
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* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Low-level exception handers, MMU support, and rewrite.
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* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
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* PowerPC 8xx modifications.
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* Copyright (c) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright 2000 MontaVista Software Inc.
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* PPC405 modifications
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* PowerPC 403GCX/405GP modifications.
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* Author: MontaVista Software, Inc.
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* frank_rowand@mvista.com or source@mvista.com
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* debbie_chu@mvista.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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#include <linux/of_fdt.h> /* for OF_DT_HEADER */
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#ifdef CONFIG_MMU
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#include <asm/setup.h> /* COMMAND_LINE_SIZE */
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#include <asm/mmu.h>
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#include <asm/processor.h>
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.data
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.global empty_zero_page
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.align 12
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empty_zero_page:
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.space 4096
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.global swapper_pg_dir
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swapper_pg_dir:
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.space 4096
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#endif /* CONFIG_MMU */
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.text
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ENTRY(_start)
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mfs r1, rmsr
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andi r1, r1, ~2
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mts rmsr, r1
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/*
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* Here is checking mechanism which check if Microblaze has msr instructions
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* We load msr and compare it with previous r1 value - if is the same,
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* msr instructions works if not - cpu don't have them.
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*/
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/* r8=0 - I have msr instr, 1 - I don't have them */
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rsubi r0, r0, 1 /* set the carry bit */
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msrclr r0, 0x4 /* try to clear it */
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/* read the carry bit, r8 will be '0' if msrclr exists */
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addik r8, r0, 0
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/* r7 may point to an FDT, or there may be one linked in.
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if it's in r7, we've got to save it away ASAP.
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We ensure r7 points to a valid FDT, just in case the bootloader
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is broken or non-existent */
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beqi r7, no_fdt_arg /* NULL pointer? don't copy */
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lw r11, r0, r7 /* Does r7 point to a */
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rsubi r11, r11, OF_DT_HEADER /* valid FDT? */
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beqi r11, _prepare_copy_fdt
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or r7, r0, r0 /* clear R7 when not valid DTB */
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bnei r11, no_fdt_arg /* No - get out of here */
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_prepare_copy_fdt:
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or r11, r0, r0 /* incremment */
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ori r4, r0, TOPHYS(_fdt_start)
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ori r3, r0, (0x4000 - 4)
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_copy_fdt:
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lw r12, r7, r11 /* r12 = r7 + r11 */
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sw r12, r4, r11 /* addr[r4 + r11] = r12 */
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addik r11, r11, 4 /* increment counting */
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bgtid r3, _copy_fdt /* loop for all entries */
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addik r3, r3, -4 /* descrement loop */
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no_fdt_arg:
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#ifdef CONFIG_MMU
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#ifndef CONFIG_CMDLINE_BOOL
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/*
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* handling command line
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* copy command line to __init_end. There is space for storing command line.
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*/
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or r6, r0, r0 /* incremment */
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ori r4, r0, __init_end /* load address of command line */
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tophys(r4,r4) /* convert to phys address */
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ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
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_copy_command_line:
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lbu r7, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */
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sb r7, r4, r6 /* addr[r4+r6]= r7*/
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addik r6, r6, 1 /* increment counting */
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bgtid r3, _copy_command_line /* loop for all entries */
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addik r3, r3, -1 /* descrement loop */
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addik r5, r4, 0 /* add new space for command line */
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tovirt(r5,r5)
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#endif /* CONFIG_CMDLINE_BOOL */
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#ifdef NOT_COMPILE
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/* save bram context */
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or r6, r0, r0 /* incremment */
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ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */
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ori r3, r0, (LMB_SIZE - 4)
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_copy_bram:
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lw r7, r0, r6 /* r7 = r0 + r6 */
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sw r7, r4, r6 /* addr[r4 + r6] = r7*/
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addik r6, r6, 4 /* increment counting */
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bgtid r3, _copy_bram /* loop for all entries */
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addik r3, r3, -4 /* descrement loop */
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#endif
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/* We have to turn on the MMU right away. */
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/*
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* Set up the initial MMU state so we can do the first level of
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* kernel initialization. This maps the first 16 MBytes of memory 1:1
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* virtual to physical.
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*/
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nop
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addik r3, r0, 63 /* Invalidate all TLB entries */
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_invalidate:
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mts rtlbx, r3
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mts rtlbhi, r0 /* flush: ensure V is clear */
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bgtid r3, _invalidate /* loop for all entries */
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addik r3, r3, -1
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/* sync */
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/*
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* We should still be executing code at physical address area
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* RAM_BASEADDR at this point. However, kernel code is at
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* a virtual address. So, set up a TLB mapping to cover this once
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* translation is enabled.
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*/
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addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
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tophys(r4,r3) /* Load the kernel physical address */
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mts rpid,r0 /* Load the kernel PID */
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nop
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bri 4
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/*
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* Configure and load two entries into TLB slots 0 and 1.
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* In case we are pinning TLBs, these are reserved in by the
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* other TLB functions. If not reserving, then it doesn't
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* matter where they are loaded.
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*/
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andi r4,r4,0xfffffc00 /* Mask off the real page number */
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ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
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andi r3,r3,0xfffffc00 /* Mask off the effective page number */
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ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
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mts rtlbx,r0 /* TLB slow 0 */
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mts rtlblo,r4 /* Load the data portion of the entry */
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mts rtlbhi,r3 /* Load the tag portion of the entry */
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addik r4, r4, 0x01000000 /* Map next 16 M entries */
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addik r3, r3, 0x01000000
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ori r6,r0,1 /* TLB slot 1 */
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mts rtlbx,r6
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mts rtlblo,r4 /* Load the data portion of the entry */
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mts rtlbhi,r3 /* Load the tag portion of the entry */
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/*
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* Load a TLB entry for LMB, since we need access to
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* the exception vectors, using a 4k real==virtual mapping.
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*/
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ori r6,r0,3 /* TLB slot 3 */
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mts rtlbx,r6
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ori r4,r0,(TLB_WR | TLB_EX)
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ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
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mts rtlblo,r4 /* Load the data portion of the entry */
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mts rtlbhi,r3 /* Load the tag portion of the entry */
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/*
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* We now have the lower 16 Meg of RAM mapped into TLB entries, and the
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* caches ready to work.
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*/
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turn_on_mmu:
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ori r15,r0,start_here
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ori r4,r0,MSR_KERNEL_VMS
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mts rmsr,r4
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nop
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rted r15,0 /* enables MMU */
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nop
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start_here:
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#endif /* CONFIG_MMU */
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/* Initialize small data anchors */
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la r13, r0, _KERNEL_SDA_BASE_
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la r2, r0, _KERNEL_SDA2_BASE_
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/* Initialize stack pointer */
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la r1, r0, init_thread_union + THREAD_SIZE - 4
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/* Initialize r31 with current task address */
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la r31, r0, init_task
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/*
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* Call platform dependent initialize function.
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* Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
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* the function.
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*/
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la r9, r0, machine_early_init
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brald r15, r9
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nop
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#ifndef CONFIG_MMU
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la r15, r0, machine_halt
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braid start_kernel
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nop
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#else
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/*
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* Initialize the MMU.
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*/
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bralid r15, mmu_init
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nop
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/* Go back to running unmapped so we can load up new values
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* and change to using our exception vectors.
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* On the MicroBlaze, all we invalidate the used TLB entries to clear
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* the old 16M byte TLB mappings.
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*/
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ori r15,r0,TOPHYS(kernel_load_context)
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ori r4,r0,MSR_KERNEL
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mts rmsr,r4
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nop
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bri 4
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rted r15,0
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nop
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/* Load up the kernel context */
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kernel_load_context:
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# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
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ori r5,r0,3
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mts rtlbx,r5
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nop
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mts rtlbhi,r0
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nop
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addi r15, r0, machine_halt
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ori r17, r0, start_kernel
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ori r4, r0, MSR_KERNEL_VMS
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mts rmsr, r4
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nop
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rted r17, 0 /* enable MMU and jump to start_kernel */
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nop
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#endif /* CONFIG_MMU */
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