1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
164 lines
4.4 KiB
C
164 lines
4.4 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* MIPS boards specific PCI support.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/gt64120.h>
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#include <asm/mips-boards/bonito64.h>
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#include <asm/mips-boards/msc01_pci.h>
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#ifdef CONFIG_MIPS_MALTA
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#include <asm/mips-boards/malta.h>
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#endif
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static struct resource bonito64_mem_resource = {
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.name = "Bonito PCI MEM",
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.start = 0x10000000UL,
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.end = 0x1bffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource bonito64_io_resource = {
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.name = "Bonito IO MEM",
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.start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */
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.end = 0x000fffffUL,
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.flags = IORESOURCE_IO,
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};
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static struct resource gt64120_mem_resource = {
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.name = "GT64120 PCI MEM",
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.start = 0x10000000UL,
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.end = 0x1bdfffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource gt64120_io_resource = {
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.name = "GT64120 IO MEM",
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#ifdef CONFIG_MIPS_ATLAS
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.start = 0x18000000UL,
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.end = 0x181fffffUL,
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#endif
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#ifdef CONFIG_MIPS_MALTA
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.start = 0x00002000UL,
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.end = 0x001fffffUL,
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#endif
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.flags = IORESOURCE_IO,
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};
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static struct resource msc_mem_resource = {
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.name = "MSC PCI MEM",
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.start = 0x10000000UL,
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.end = 0x1fffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource msc_io_resource = {
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.name = "MSC IO MEM",
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.start = 0x00002000UL,
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.end = 0x007fffffUL,
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.flags = IORESOURCE_IO,
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};
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extern struct pci_ops bonito64_pci_ops;
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extern struct pci_ops gt64120_pci_ops;
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extern struct pci_ops msc_pci_ops;
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static struct pci_controller bonito64_controller = {
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.pci_ops = &bonito64_pci_ops,
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.io_resource = &bonito64_io_resource,
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.mem_resource = &bonito64_mem_resource,
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.mem_offset = 0x10000000UL,
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.io_offset = 0x00000000UL,
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};
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static struct pci_controller gt64120_controller = {
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.pci_ops = >64120_pci_ops,
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.io_resource = >64120_io_resource,
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.mem_resource = >64120_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_offset = 0x00000000UL,
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};
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static struct pci_controller msc_controller = {
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.pci_ops = &msc_pci_ops,
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.io_resource = &msc_io_resource,
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.mem_resource = &msc_mem_resource,
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.mem_offset = 0x10000000UL,
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.io_offset = 0x00000000UL,
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};
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static int __init pcibios_init(void)
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{
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struct pci_controller *controller;
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switch (mips_revision_corid) {
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case MIPS_REVISION_CORID_QED_RM5261:
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case MIPS_REVISION_CORID_CORE_LV:
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case MIPS_REVISION_CORID_CORE_FPGA:
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case MIPS_REVISION_CORID_CORE_FPGAR2:
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/*
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* Due to a bug in the Galileo system controller, we need
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* to setup the PCI BAR for the Galileo internal registers.
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* This should be done in the bios/bootprom and will be
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* fixed in a later revision of YAMON (the MIPS boards
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* boot prom).
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*/
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
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(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
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((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
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GT_PCI0_CFGADDR_CONFIGEN_BIT );
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/* Perform the write */
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GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
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controller = >64120_controller;
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break;
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case MIPS_REVISION_CORID_BONITO64:
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case MIPS_REVISION_CORID_CORE_20K:
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case MIPS_REVISION_CORID_CORE_EMUL_BON:
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controller = &bonito64_controller;
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break;
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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controller = &msc_controller;
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break;
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default:
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return 1;
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}
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ioport_resource.end = controller->io_resource->end;
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register_pci_controller (controller);
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return 0;
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}
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early_initcall(pcibios_init);
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