6a01f23033
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
174 lines
5.3 KiB
C
174 lines
5.3 KiB
C
/*
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* File: include/asm-blackfin/mach-bf533/defBF532.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _BF533_IRQ_H_
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#define _BF533_IRQ_H_
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/*
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* Interrupt source definitions
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Event Source Core Event Name
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Core Emulation **
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Events (highest priority) EMU 0
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Reset RST 1
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NMI NMI 2
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Exception EVX 3
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Reserved -- 4
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Hardware Error IVHW 5
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Core Timer IVTMR 6 *
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PLL Wakeup Interrupt IVG7 7
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DMA Error (generic) IVG7 8
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PPI Error Interrupt IVG7 9
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SPORT0 Error Interrupt IVG7 10
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SPORT1 Error Interrupt IVG7 11
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SPI Error Interrupt IVG7 12
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UART Error Interrupt IVG7 13
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RTC Interrupt IVG8 14
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DMA0 Interrupt (PPI) IVG8 15
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DMA1 (SPORT0 RX) IVG9 16
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DMA2 (SPORT0 TX) IVG9 17
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DMA3 (SPORT1 RX) IVG9 18
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DMA4 (SPORT1 TX) IVG9 19
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DMA5 (PPI) IVG10 20
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DMA6 (UART RX) IVG10 21
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DMA7 (UART TX) IVG10 22
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Timer0 IVG11 23
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Timer1 IVG11 24
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Timer2 IVG11 25
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PF Interrupt A IVG12 26
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PF Interrupt B IVG12 27
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DMA8/9 Interrupt IVG13 28
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DMA10/11 Interrupt IVG13 29
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Watchdog Timer IVG13 30
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Softirq IVG14 31
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System Call --
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(lowest priority) IVG15 32 *
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*/
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#define SYS_IRQS 31
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#define NR_PERI_INTS 24
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/* The ABSTRACT IRQ definitions */
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/** the first seven of the following are fixed, the rest you change if you need to **/
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#define IRQ_EMU 0 /*Emulation */
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#define IRQ_RST 1 /*reset */
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#define IRQ_NMI 2 /*Non Maskable */
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#define IRQ_EVX 3 /*Exception */
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#define IRQ_UNUSED 4 /*- unused interrupt*/
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#define IRQ_HWERR 5 /*Hardware Error */
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#define IRQ_CORETMR 6 /*Core timer */
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#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
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#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
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#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
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#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
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#define IRQ_RTC 14 /*RTC Interrupt */
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#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
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#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
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#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
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#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
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#define IRQ_TIMER0 23 /*Timer 0 */
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#define IRQ_TIMER1 24 /*Timer 1 */
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#define IRQ_TIMER2 25 /*Timer 2 */
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#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
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#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
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#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
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#define IRQ_WATCH 30 /*Watch Dog Timer */
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#define IRQ_PF0 33
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#define IRQ_PF1 34
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#define IRQ_PF2 35
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#define IRQ_PF3 36
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#define IRQ_PF4 37
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#define IRQ_PF5 38
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#define IRQ_PF6 39
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#define IRQ_PF7 40
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#define IRQ_PF8 41
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#define IRQ_PF9 42
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#define IRQ_PF10 43
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#define IRQ_PF11 44
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#define IRQ_PF12 45
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#define IRQ_PF13 46
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#define IRQ_PF14 47
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#define IRQ_PF15 48
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#define GPIO_IRQ_BASE IRQ_PF0
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#define NR_IRQS (IRQ_PF15+1)
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#define IVG7 7
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#define IVG8 8
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#define IVG9 9
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#define IVG10 10
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#define IVG11 11
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#define IVG12 12
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#define IVG13 13
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#define IVG14 14
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#define IVG15 15
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/* IAR0 BIT FIELDS*/
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#define RTC_ERROR_POS 28
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#define UART_ERROR_POS 24
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#define SPORT1_ERROR_POS 20
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#define SPI_ERROR_POS 16
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#define SPORT0_ERROR_POS 12
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#define PPI_ERROR_POS 8
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#define DMA_ERROR_POS 4
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#define PLLWAKE_ERROR_POS 0
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/* IAR1 BIT FIELDS*/
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#define DMA7_UARTTX_POS 28
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#define DMA6_UARTRX_POS 24
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#define DMA5_SPI_POS 20
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#define DMA4_SPORT1TX_POS 16
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#define DMA3_SPORT1RX_POS 12
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#define DMA2_SPORT0TX_POS 8
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#define DMA1_SPORT0RX_POS 4
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#define DMA0_PPI_POS 0
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/* IAR2 BIT FIELDS*/
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#define WDTIMER_POS 28
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#define MEMDMA1_POS 24
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#define MEMDMA0_POS 20
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#define PFB_POS 16
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#define PFA_POS 12
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#define TIMER2_POS 8
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#define TIMER1_POS 4
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#define TIMER0_POS 0
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#endif /* _BF533_IRQ_H_ */
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