2925aba422
Historically plat_mem_setup did the entire platform initialization. This was rather impractical because it meant plat_mem_setup had to get away without any kind of memory allocator. To keep old code from breaking plat_setup was just renamed to plat_setup and a second platform initialization hook for anything else was introduced. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
161 lines
4.5 KiB
C
161 lines
4.5 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Galileo EV96100 setup.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This file was derived from Carsten Langgaard's
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* arch/mips/mips-boards/atlas/atlas_setup.c.
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/string.h>
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#include <linux/ctype.h>
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#include <linux/pci.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/irq.h>
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#include <asm/delay.h>
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#include <asm/gt64120.h>
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#include <asm/galileo-boards/ev96100int.h>
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extern char *__init prom_getcmdline(void);
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extern void mips_reboot_setup(void);
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unsigned char mac_0_1[12];
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void __init plat_mem_setup(void)
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{
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unsigned int config = read_c0_config();
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unsigned int status = read_c0_status();
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unsigned int info = read_c0_info();
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u32 tmp;
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char *argptr;
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clear_c0_status(ST0_FR);
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if (config & 0x8)
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printk("Secondary cache is enabled\n");
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else
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printk("Secondary cache is disabled\n");
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if (status & (1 << 27))
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printk("User-mode cache ops enabled\n");
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else
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printk("User-mode cache ops disabled\n");
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printk("CP0 info reg: %x\n", (unsigned) info);
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if (info & (1 << 28))
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printk("burst mode Scache RAMS\n");
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else
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printk("pipelined Scache RAMS\n");
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if (info & 0x1)
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printk("Atomic Enable is set\n");
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argptr = prom_getcmdline();
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#ifdef CONFIG_SERIAL_CONSOLE
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if (strstr(argptr, "console=") == NULL) {
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argptr = prom_getcmdline();
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strcat(argptr, " console=ttyS0,115200");
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}
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#endif
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mips_reboot_setup();
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set_io_port_base(KSEG1);
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ioport_resource.start = GT_PCI_IO_BASE;
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ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff;
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#ifdef CONFIG_BLK_DEV_INITRD
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ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
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#endif
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/*
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* Setup GT controller master bit so we can do config cycles
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*/
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/* Clear cause register bits */
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GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
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GT_INTRCAUSE_TARABORT0_BIT));
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/* Setup address */
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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udelay(2);
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tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
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tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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udelay(2);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
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/* Setup address */
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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udelay(2);
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tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
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}
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unsigned short get_gt_devid(void)
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{
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u32 gt_devid;
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/* Figure out if this is a gt96100 or gt96100A */
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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udelay(4);
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gt_devid = GT_READ(GT_PCI0_CFGDATA_OFS);
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return gt_devid >> 16;
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}
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