12458ea06e
This patch adds new version of the PPC440SPe ADMA driver. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
94 lines
2.1 KiB
Plaintext
94 lines
2.1 KiB
Plaintext
PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
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Device nodes needed for operation of the ppc440spe-adma driver
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are specified hereby. These are I2O/DMA, DMA and XOR nodes
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for DMA engines and Memory Queue Module node. The latter is used
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by ADMA driver for configuration of RAID-6 H/W capabilities of
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the PPC440SPe. In addition to the nodes and properties described
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below, the ranges property of PLB node must specify ranges for
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DMA devices.
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i) The I2O node
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Required properties:
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- compatible : "ibm,i2o-440spe";
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- reg : <registers mapping>
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- dcr-reg : <DCR registers range>
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Example:
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I2O: i2o@400100000 {
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compatible = "ibm,i2o-440spe";
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reg = <0x00000004 0x00100000 0x100>;
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dcr-reg = <0x060 0x020>;
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};
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ii) The DMA node
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Required properties:
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- compatible : "ibm,dma-440spe";
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- cell-index : 1 cell, hardware index of the DMA engine
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(typically 0x0 and 0x1 for DMA0 and DMA1)
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- reg : <registers mapping>
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- dcr-reg : <DCR registers range>
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- interrupts : <interrupt mapping for DMA0/1 interrupts sources:
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2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
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and DMA Error IRQ (on UIC1). The latter is common
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for both DMA engines>.
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- interrupt-parent : needed for interrupt mapping
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Example:
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DMA0: dma0@400100100 {
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compatible = "ibm,dma-440spe";
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cell-index = <0>;
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reg = <0x00000004 0x00100100 0x100>;
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dcr-reg = <0x060 0x020>;
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interrupt-parent = <&DMA0>;
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interrupts = <0 1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <
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0 &UIC0 0x14 4
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1 &UIC1 0x16 4>;
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};
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iii) XOR Accelerator node
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Required properties:
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- compatible : "amcc,xor-accelerator";
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- reg : <registers mapping>
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- interrupts : <interrupt mapping for XOR interrupt source>
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- interrupt-parent : for interrupt mapping
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Example:
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xor-accel@400200000 {
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compatible = "amcc,xor-accelerator";
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reg = <0x00000004 0x00200000 0x400>;
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interrupt-parent = <&UIC1>;
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interrupts = <0x1f 4>;
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};
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iv) Memory Queue Module node
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Required properties:
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- compatible : "ibm,mq-440spe";
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- dcr-reg : <DCR registers range>
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Example:
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MQ0: mq {
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compatible = "ibm,mq-440spe";
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dcr-reg = <0x040 0x020>;
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};
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