229 lines
6.0 KiB
C
229 lines
6.0 KiB
C
/*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2004 Richard Curnow
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* Support functions for the SH5 PCI hardware.
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*/
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#include <linux/kernel.h>
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#include <linux/rwsem.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <asm/cpu/irq.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include "pci-sh5.h"
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unsigned long pcicr_virt;
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unsigned long PCI_IO_AREA;
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/* Rounds a number UP to the nearest power of two. Used for
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* sizing the PCI window.
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*/
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static u32 __init r2p2(u32 num)
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{
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int i = 31;
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u32 tmp = num;
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if (num == 0)
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return 0;
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do {
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if (tmp & (1 << 31))
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break;
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i--;
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tmp <<= 1;
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} while (i >= 0);
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tmp = 1 << i;
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/* If the original number isn't a power of 2, round it up */
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if (tmp != num)
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tmp <<= 1;
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return tmp;
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}
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static irqreturn_t pcish5_err_irq(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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unsigned pci_int, pci_air, pci_cir, pci_aint;
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pci_int = SH5PCI_READ(INT);
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pci_cir = SH5PCI_READ(CIR);
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pci_air = SH5PCI_READ(AIR);
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if (pci_int) {
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printk("PCI INTERRUPT (at %08llx)!\n", regs->pc);
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printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
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printk("PCI AIR -> 0x%x\n", pci_air);
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printk("PCI CIR -> 0x%x\n", pci_cir);
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SH5PCI_WRITE(INT, ~0);
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}
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pci_aint = SH5PCI_READ(AINT);
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if (pci_aint) {
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printk("PCI ARB INTERRUPT!\n");
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printk("PCI AINT -> 0x%x\n", pci_aint);
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printk("PCI AIR -> 0x%x\n", pci_air);
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printk("PCI CIR -> 0x%x\n", pci_cir);
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SH5PCI_WRITE(AINT, ~0);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
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{
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printk("SERR IRQ\n");
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return IRQ_NONE;
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}
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int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
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{
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u32 lsr0;
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u32 uval;
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if (request_irq(IRQ_ERR, pcish5_err_irq,
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IRQF_DISABLED, "PCI Error",NULL) < 0) {
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printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n");
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return -EINVAL;
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}
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if (request_irq(IRQ_SERR, pcish5_serr_irq,
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IRQF_DISABLED, "PCI SERR interrupt", NULL) < 0) {
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printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n");
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return -EINVAL;
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}
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pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR");
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if (!pcicr_virt) {
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panic("Unable to remap PCICR\n");
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}
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PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO");
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if (!PCI_IO_AREA) {
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panic("Unable to remap PCIIO\n");
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}
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/* Clear snoop registers */
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SH5PCI_WRITE(CSCR0, 0);
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SH5PCI_WRITE(CSCR1, 0);
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/* Switch off interrupts */
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SH5PCI_WRITE(INTM, 0);
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SH5PCI_WRITE(AINTM, 0);
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SH5PCI_WRITE(PINTM, 0);
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/* Set bus active, take it out of reset */
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uval = SH5PCI_READ(CR);
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/* Set command Register */
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SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE |
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CR_PFCS | CR_BMAM);
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uval=SH5PCI_READ(CR);
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/* Allow it to be a master */
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/* NB - WE DISABLE I/O ACCESS to stop overlap */
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/* set WAIT bit to enable stepping, an attempt to improve stability */
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SH5PCI_WRITE_SHORT(CSR_CMD,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_WAIT);
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/*
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** Set translation mapping memory in order to convert the address
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** used for the main bus, to the PCI internal address.
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*/
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SH5PCI_WRITE(MBR,0x40000000);
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/* Always set the max size 512M */
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SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024));
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/*
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** I/O addresses are mapped at internal PCI specific address
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** as is described into the configuration bridge table.
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** These are changed to 0, to allow cards that have legacy
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** io such as vga to function correctly. We set the SH5 IOBAR to
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** 256K, which is a bit big as we can only have 64K of address space
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*/
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SH5PCI_WRITE(IOBR,0x0);
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/* Set up a 256K window. Totally pointless waste of address space */
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SH5PCI_WRITE(IOBMR,0);
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/* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec.
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* Ideally, we would want to map the I/O region somewhere, but it
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* is so big this is not that easy!
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*/
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SH5PCI_WRITE(CSR_IBAR0,~0);
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/* Set memory size value */
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memSize = memory_end - memory_start;
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/* Now we set up the mbars so the PCI bus can see the memory of
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* the machine */
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if (memSize < (1024 * 1024)) {
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printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n",
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memSize);
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return -EINVAL;
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}
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/* Set LSR 0 */
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lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 :
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((r2p2(memSize) - 0x100000) | 0x1);
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SH5PCI_WRITE(LSR0, lsr0);
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/* Set MBAR 0 */
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SH5PCI_WRITE(CSR_MBAR0, memory_start);
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SH5PCI_WRITE(LAR0, memory_start);
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SH5PCI_WRITE(CSR_MBAR1,0);
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SH5PCI_WRITE(LAR1,0);
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SH5PCI_WRITE(LSR1,0);
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/* Enable the PCI interrupts on the device */
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SH5PCI_WRITE(INTM, ~0);
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SH5PCI_WRITE(AINTM, ~0);
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SH5PCI_WRITE(PINTM, ~0);
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return 0;
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}
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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int i;
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if (dev) {
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for (i= 0; i < 3; i++) {
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bus->resource[i] =
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&dev->resource[PCI_BRIDGE_RESOURCES+i];
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bus->resource[i]->name = bus->name;
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}
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bus->resource[0]->flags |= IORESOURCE_IO;
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bus->resource[1]->flags |= IORESOURCE_MEM;
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/* For now, propagate host limits to the bus;
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* we'll adjust them later. */
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bus->resource[0]->end = 64*1024 - 1 ;
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bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
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bus->resource[0]->start = PCIBIOS_MIN_IO;
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bus->resource[1]->start = PCIBIOS_MIN_MEM;
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/* Turn off downstream PF memory address range by default */
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bus->resource[2]->start = 1024*1024;
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bus->resource[2]->end = bus->resource[2]->start - 1;
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}
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}
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