ef1ea0b424
Currently keeping it at 1500 bytes or below since jumbo frames need special checksum offload on TX. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
185 lines
5.7 KiB
C
185 lines
5.7 KiB
C
/*
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* Copyright (C) 2006 PA Semi, Inc
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*
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* Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
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* hardware register layouts.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef PASEMI_MAC_H
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#define PASEMI_MAC_H
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#include <linux/ethtool.h>
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#include <linux/netdevice.h>
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#include <linux/spinlock.h>
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#include <linux/phy.h>
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#define MAX_LRO_DESCRIPTORS 8
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struct pasemi_mac_txring {
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struct pasemi_dmachan chan; /* Must be first */
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spinlock_t lock;
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unsigned int size;
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unsigned int next_to_fill;
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unsigned int next_to_clean;
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struct pasemi_mac_buffer *ring_info;
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struct pasemi_mac *mac; /* Needed in intr handler */
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struct timer_list clean_timer;
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};
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struct pasemi_mac_rxring {
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struct pasemi_dmachan chan; /* Must be first */
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spinlock_t lock;
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u64 *buffers; /* RX interface buffer ring */
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dma_addr_t buf_dma;
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unsigned int size;
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unsigned int next_to_fill;
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unsigned int next_to_clean;
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struct pasemi_mac_buffer *ring_info;
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struct pasemi_mac *mac; /* Needed in intr handler */
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};
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struct pasemi_mac {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct pci_dev *dma_pdev;
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struct pci_dev *iob_pdev;
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struct phy_device *phydev;
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struct napi_struct napi;
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int bufsz; /* RX ring buffer size */
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u8 type;
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#define MAC_TYPE_GMAC 1
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#define MAC_TYPE_XAUI 2
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u32 dma_if;
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u8 mac_addr[6];
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struct net_lro_mgr lro_mgr;
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struct net_lro_desc lro_desc[MAX_LRO_DESCRIPTORS];
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struct timer_list rxtimer;
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unsigned int lro_max_aggr;
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struct pasemi_mac_txring *tx;
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struct pasemi_mac_rxring *rx;
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char tx_irq_name[10]; /* "eth%d tx" */
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char rx_irq_name[10]; /* "eth%d rx" */
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int link;
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int speed;
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int duplex;
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unsigned int msg_enable;
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char phy_id[BUS_ID_SIZE];
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};
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/* Software status descriptor (ring_info) */
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struct pasemi_mac_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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};
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/* PCI register offsets and formats */
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/* MAC CFG register offsets */
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enum {
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PAS_MAC_CFG_PCFG = 0x80,
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PAS_MAC_CFG_MACCFG = 0x84,
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PAS_MAC_CFG_ADR0 = 0x8c,
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PAS_MAC_CFG_ADR1 = 0x90,
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PAS_MAC_CFG_TXP = 0x98,
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PAS_MAC_IPC_CHNL = 0x208,
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};
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/* MAC CFG register fields */
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#define PAS_MAC_CFG_PCFG_PE 0x80000000
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#define PAS_MAC_CFG_PCFG_CE 0x40000000
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#define PAS_MAC_CFG_PCFG_BU 0x20000000
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#define PAS_MAC_CFG_PCFG_TT 0x10000000
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#define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
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#define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
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#define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
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#define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
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#define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
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#define PAS_MAC_CFG_PCFG_T24 0x02000000
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#define PAS_MAC_CFG_PCFG_PR 0x01000000
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#define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
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#define PAS_MAC_CFG_PCFG_CRO_S 16
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#define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
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#define PAS_MAC_CFG_PCFG_IPO_S 8
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#define PAS_MAC_CFG_PCFG_S1 0x00000080
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#define PAS_MAC_CFG_PCFG_IO_M 0x00000060
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#define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
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#define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
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#define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
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#define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
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#define PAS_MAC_CFG_PCFG_LP 0x00000010
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#define PAS_MAC_CFG_PCFG_TS 0x00000008
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#define PAS_MAC_CFG_PCFG_HD 0x00000004
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#define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
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#define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
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#define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
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#define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
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#define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
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#define PAS_MAC_CFG_MACCFG_TXT_M 0x70000000
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#define PAS_MAC_CFG_MACCFG_TXT_S 28
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#define PAS_MAC_CFG_MACCFG_PRES_M 0x0f000000
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#define PAS_MAC_CFG_MACCFG_PRES_S 24
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#define PAS_MAC_CFG_MACCFG_MAXF_M 0x00ffff00
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#define PAS_MAC_CFG_MACCFG_MAXF_S 8
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#define PAS_MAC_CFG_MACCFG_MAXF(x) (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \
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PAS_MAC_CFG_MACCFG_MAXF_M)
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#define PAS_MAC_CFG_MACCFG_MINF_M 0x000000ff
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#define PAS_MAC_CFG_MACCFG_MINF_S 0
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#define PAS_MAC_CFG_TXP_FCF 0x01000000
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#define PAS_MAC_CFG_TXP_FCE 0x00800000
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#define PAS_MAC_CFG_TXP_FC 0x00400000
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#define PAS_MAC_CFG_TXP_FPC_M 0x00300000
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#define PAS_MAC_CFG_TXP_FPC_S 20
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#define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
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PAS_MAC_CFG_TXP_FPC_M)
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#define PAS_MAC_CFG_TXP_RT 0x00080000
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#define PAS_MAC_CFG_TXP_BL 0x00040000
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#define PAS_MAC_CFG_TXP_SL_M 0x00030000
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#define PAS_MAC_CFG_TXP_SL_S 16
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#define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
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PAS_MAC_CFG_TXP_SL_M)
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#define PAS_MAC_CFG_TXP_COB_M 0x0000f000
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#define PAS_MAC_CFG_TXP_COB_S 12
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#define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
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PAS_MAC_CFG_TXP_COB_M)
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#define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
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#define PAS_MAC_CFG_TXP_TIFT_S 8
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#define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
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PAS_MAC_CFG_TXP_TIFT_M)
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#define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
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#define PAS_MAC_CFG_TXP_TIFG_S 0
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#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
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PAS_MAC_CFG_TXP_TIFG_M)
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#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
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#define PAS_MAC_IPC_CHNL_DCHNO_S 16
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#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
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PAS_MAC_IPC_CHNL_DCHNO_M)
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#define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
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#define PAS_MAC_IPC_CHNL_BCH_S 0
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#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
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PAS_MAC_IPC_CHNL_BCH_M)
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#endif /* PASEMI_MAC_H */
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