7e41e7b3f0
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
575 lines
16 KiB
C
575 lines
16 KiB
C
/*
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* Board setup routines for IBM Chestnut
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*
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* Author: <source@mvista.com>
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*
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* <2004> (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/blkdev.h>
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#include <linux/console.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <linux/mtd/physmap.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/time.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/hw_irq.h>
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#include <asm/machdep.h>
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#include <asm/kgdb.h>
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#include <asm/bootinfo.h>
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#include <asm/mv64x60.h>
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#include <platforms/chestnut.h>
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static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
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static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
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static mv64x60_handle_t bh;
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extern void gen550_progress(char *, unsigned short);
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extern void gen550_init(int, struct uart_port *);
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extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
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#define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
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BIT(MV64x60_CPU2DEV_1_WIN) | \
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BIT(MV64x60_CPU2DEV_2_WIN) | \
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BIT(MV64x60_CPU2DEV_3_WIN) | \
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BIT(MV64x60_CPU2BOOT_WIN))
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/**************************************************************************
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* FUNCTION: chestnut_calibrate_decr
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*
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* DESCRIPTION: initialize decrementer interrupt frequency (used as system
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* timer)
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*
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****/
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static void __init
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chestnut_calibrate_decr(void)
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{
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ulong freq;
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freq = CHESTNUT_BUS_SPEED / 4;
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printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
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freq/1000000, freq%1000000);
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tb_ticks_per_jiffy = freq / HZ;
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tb_to_us = mulhwu_scale_factor(freq, 1000000);
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}
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static int
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chestnut_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: IBM\n");
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seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
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return 0;
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}
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/**************************************************************************
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* FUNCTION: chestnut_find_end_of_memory
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*
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* DESCRIPTION: ppc_md memory size callback
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*
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****/
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unsigned long __init
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chestnut_find_end_of_memory(void)
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{
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static int mem_size = 0;
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if (mem_size == 0) {
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mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
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MV64x60_TYPE_MV64460);
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}
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return mem_size;
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}
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#if defined(CONFIG_SERIAL_8250)
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static void __init
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chestnut_early_serial_map(void)
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{
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struct uart_port port;
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/* Setup serial port access */
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memset(&port, 0, sizeof(port));
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port.uartclk = BASE_BAUD * 16;
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port.irq = UART0_INT;
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port.flags = STD_COM_FLAGS | UPF_IOREMAP;
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port.iotype = UPIO_MEM;
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port.mapbase = CHESTNUT_UART0_IO_BASE;
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port.regshift = 0;
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if (early_serial_setup(&port) != 0)
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printk("Early serial init of port 0 failed\n");
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/* Assume early_serial_setup() doesn't modify serial_req */
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port.line = 1;
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port.irq = UART1_INT;
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port.mapbase = CHESTNUT_UART1_IO_BASE;
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if (early_serial_setup(&port) != 0)
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printk("Early serial init of port 1 failed\n");
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}
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#endif
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/**************************************************************************
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* FUNCTION: chestnut_map_irq
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*
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* DESCRIPTION: 0 return since PCI IRQs not needed
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*
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****/
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static int __init
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chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] = {
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{CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
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CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
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{CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
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CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
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{CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
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CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
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{CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
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CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
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};
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const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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/**************************************************************************
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* FUNCTION: chestnut_setup_bridge
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*
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* DESCRIPTION: initalize board-specific settings on the MV64360
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*
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****/
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static void __init
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chestnut_setup_bridge(void)
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{
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struct mv64x60_setup_info si;
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int i;
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if ( ppc_md.progress )
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ppc_md.progress("chestnut_setup_bridge: enter", 0);
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memset(&si, 0, sizeof(si));
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si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
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/* setup only PCI bus 0 (bus 1 not used) */
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si.pci_0.enable_bus = 1;
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si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
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si.pci_0.pci_io.pci_base_hi = 0;
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si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
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si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
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si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
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si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
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si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
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si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
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si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
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si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
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si.pci_0.pci_cmd_bits = 0;
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si.pci_0.latency_timer = 0x80;
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for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
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#if defined(CONFIG_NOT_COHERENT_CACHE)
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si.cpu_prot_options[i] = 0;
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si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
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si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
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si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
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si.pci_1.acc_cntl_options[i] =
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MV64360_PCI_ACC_CNTL_SNOOP_NONE |
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MV64360_PCI_ACC_CNTL_SWAP_NONE |
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MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
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MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
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#else
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si.cpu_prot_options[i] = 0;
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si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
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si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
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si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
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si.pci_1.acc_cntl_options[i] =
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MV64360_PCI_ACC_CNTL_SNOOP_WB |
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MV64360_PCI_ACC_CNTL_SWAP_NONE |
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MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
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MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
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#endif
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}
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/* Lookup host bridge - on CPU 0 - no SMP support */
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if (mv64x60_init(&bh, &si)) {
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printk("\n\nPCI Bridge initialization failed!\n");
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}
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pci_dram_offset = 0;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = chestnut_map_irq;
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ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
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mv64x60_set_bus(&bh, 0, 0);
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bh.hose_a->first_busno = 0;
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bh.hose_a->last_busno = 0xff;
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bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
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}
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void __init
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chestnut_setup_peripherals(void)
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{
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
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CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
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CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
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CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
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cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
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CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
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CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
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CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
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#ifdef CONFIG_NOT_COHERENT_CACHE
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mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
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#else
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mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
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#endif
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sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
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memset(sram_base, 0, MV64360_SRAM_SIZE);
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/*
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* Configure MPP pins for PCI DMA
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*
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* PCI Slot GNT pin REQ pin
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* 0 MPP16 MPP17
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* 1 MPP18 MPP19
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* 2 MPP20 MPP21
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* 3 MPP22 MPP23
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*/
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mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
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(0x1 << 0) | /* MPPSel16 PCI0_GNT[0] */
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(0x1 << 4) | /* MPPSel17 PCI0_REQ[0] */
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(0x1 << 8) | /* MPPSel18 PCI0_GNT[1] */
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(0x1 << 12) | /* MPPSel19 PCI0_REQ[1] */
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(0x1 << 16) | /* MPPSel20 PCI0_GNT[2] */
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(0x1 << 20) | /* MPPSel21 PCI0_REQ[2] */
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(0x1 << 24) | /* MPPSel22 PCI0_GNT[3] */
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(0x1 << 28)); /* MPPSel23 PCI0_REQ[3] */
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/*
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* Set unused MPP pins for output, as per schematic note
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*
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* Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
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* MPP09, MPP10, MPP13, MPP14, MPP15
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*/
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mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
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(0xf << 4) | /* MPPSel01 GPIO[1] */
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(0xf << 8) | /* MPPSel02 GPIO[2] */
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(0xf << 16) | /* MPPSel04 GPIO[4] */
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(0xf << 20) | /* MPPSel05 GPIO[5] */
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(0xf << 24)); /* MPPSel06 GPIO[6] */
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mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
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(0xf << 4) | /* MPPSel09 GPIO[9] */
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(0xf << 8) | /* MPPSel10 GPIO[10] */
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(0xf << 20) | /* MPPSel13 GPIO[13] */
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(0xf << 24) | /* MPPSel14 GPIO[14] */
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(0xf << 28)); /* MPPSel15 GPIO[15] */
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mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
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BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) |
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BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15));
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/*
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* Configure the following MPP pins to indicate a level
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* triggered interrupt
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*
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* MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
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* MPP25 - UART A (high)
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* MPP26 - UART B (high)
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* MPP28 - PCI Slot 3 (low)
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* MPP29 - PCI Slot 2 (low)
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* MPP30 - PCI Slot 1 (low)
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* MPP31 - PCI Slot 0 (low)
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*/
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mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
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BIT(3) | BIT(2) | BIT(1) | BIT(0) | /* MPP 24 */
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BIT(7) | BIT(6) | BIT(5) | BIT(4) | /* MPP 25 */
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BIT(11) | BIT(10) | BIT(9) | BIT(8) | /* MPP 26 */
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BIT(19) | BIT(18) | BIT(17) | BIT(16) | /* MPP 28 */
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BIT(23) | BIT(22) | BIT(21) | BIT(20) | /* MPP 29 */
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BIT(27) | BIT(26) | BIT(25) | BIT(24) | /* MPP 30 */
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BIT(31) | BIT(30) | BIT(29) | BIT(28)); /* MPP 31 */
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/*
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* Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
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* 31 (low) interrupt polarity input signal and level triggered
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*/
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mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
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mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
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BIT(28) | BIT(29) | BIT(30) | BIT(31));
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mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
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BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
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BIT(31));
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/* Config GPP interrupt controller to respond to level trigger */
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mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
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/*
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* Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
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*/
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mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
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~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
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BIT(31)));
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mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
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BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
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BIT(31));
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/*
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* Dismiss and then enable interrupt on CPU #0 high cause register
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* BIT27 summarizes GPP interrupts 24-31
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*/
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mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
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if (ppc_md.progress)
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ppc_md.progress("chestnut_setup_bridge: exit", 0);
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}
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/**************************************************************************
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* FUNCTION: chestnut_setup_arch
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*
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* DESCRIPTION: ppc_md machine configuration callback
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*
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****/
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static void __init
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chestnut_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("chestnut_setup_arch: enter", 0);
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000 / HZ;
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/* if the time base value is greater than bus freq/4 (the TB and
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* decrementer tick rate) + signed integer rollover value, we
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* can spend a fair amount of time waiting for the rollover to
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* happen. To get around this, initialize the time base register
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* to a "safe" value.
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*/
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set_tb(0, 0);
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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/*
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* Set up the L2CR register.
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*/
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_set_L2CR(_get_L2CR() | L2CR_L2E);
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chestnut_setup_bridge();
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chestnut_setup_peripherals();
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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#if defined(CONFIG_SERIAL_8250)
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chestnut_early_serial_map();
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#endif
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/* Identify the system */
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printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
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printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
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" (source@mvista.com)\n");
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if (ppc_md.progress)
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ppc_md.progress("chestnut_setup_arch: exit", 0);
|
|
}
|
|
|
|
#ifdef CONFIG_MTD_PHYSMAP
|
|
static struct mtd_partition ptbl;
|
|
|
|
static int __init
|
|
chestnut_setup_mtd(void)
|
|
{
|
|
memset(&ptbl, 0, sizeof(ptbl));
|
|
|
|
ptbl.name = "User FS";
|
|
ptbl.size = CHESTNUT_32BIT_SIZE;
|
|
|
|
physmap_map.size = CHESTNUT_32BIT_SIZE;
|
|
physmap_set_partitions(&ptbl, 1);
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(chestnut_setup_mtd);
|
|
#endif
|
|
|
|
/**************************************************************************
|
|
* FUNCTION: chestnut_restart
|
|
*
|
|
* DESCRIPTION: ppc_md machine reset callback
|
|
* reset the board via the CPLD command register
|
|
*
|
|
****/
|
|
static void
|
|
chestnut_restart(char *cmd)
|
|
{
|
|
volatile ulong i = 10000000;
|
|
|
|
local_irq_disable();
|
|
|
|
/*
|
|
* Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
|
|
*
|
|
* MPP24 - board reset
|
|
*/
|
|
writeb(0x1, cpld_base + 3);
|
|
|
|
/* GPP pin tied to MPP earlier */
|
|
mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
|
|
|
|
while (i-- > 0);
|
|
panic("restart failed\n");
|
|
}
|
|
|
|
static void
|
|
chestnut_halt(void)
|
|
{
|
|
local_irq_disable();
|
|
for (;;);
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
static void
|
|
chestnut_power_off(void)
|
|
{
|
|
chestnut_halt();
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
/**************************************************************************
|
|
* FUNCTION: chestnut_map_io
|
|
*
|
|
* DESCRIPTION: configure fixed memory-mapped IO
|
|
*
|
|
****/
|
|
static void __init
|
|
chestnut_map_io(void)
|
|
{
|
|
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
|
|
io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
|
|
_PAGE_IO);
|
|
#endif
|
|
}
|
|
|
|
/**************************************************************************
|
|
* FUNCTION: chestnut_set_bat
|
|
*
|
|
* DESCRIPTION: configures a (temporary) bat mapping for early access to
|
|
* device I/O
|
|
*
|
|
****/
|
|
static __inline__ void
|
|
chestnut_set_bat(void)
|
|
{
|
|
mb();
|
|
mtspr(SPRN_DBAT3U, 0xf0001ffe);
|
|
mtspr(SPRN_DBAT3L, 0xf000002a);
|
|
mb();
|
|
}
|
|
|
|
/**************************************************************************
|
|
* FUNCTION: platform_init
|
|
*
|
|
* DESCRIPTION: main entry point for configuring board-specific machine
|
|
* callbacks
|
|
*
|
|
****/
|
|
void __init
|
|
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7)
|
|
{
|
|
parse_bootinfo(find_bootinfo());
|
|
|
|
/* Copy the kernel command line arguments to a safe place. */
|
|
|
|
if (r6) {
|
|
*(char *) (r7 + KERNELBASE) = 0;
|
|
strcpy(cmd_line, (char *) (r6 + KERNELBASE));
|
|
}
|
|
|
|
isa_mem_base = 0;
|
|
|
|
ppc_md.setup_arch = chestnut_setup_arch;
|
|
ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
|
|
ppc_md.init_IRQ = mv64360_init_irq;
|
|
ppc_md.get_irq = mv64360_get_irq;
|
|
ppc_md.init = NULL;
|
|
|
|
ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
|
|
ppc_md.setup_io_mappings = chestnut_map_io;
|
|
|
|
ppc_md.restart = chestnut_restart;
|
|
ppc_md.power_off = chestnut_power_off;
|
|
ppc_md.halt = chestnut_halt;
|
|
|
|
ppc_md.time_init = NULL;
|
|
ppc_md.set_rtc_time = NULL;
|
|
ppc_md.get_rtc_time = NULL;
|
|
ppc_md.calibrate_decr = chestnut_calibrate_decr;
|
|
|
|
ppc_md.nvram_read_val = NULL;
|
|
ppc_md.nvram_write_val = NULL;
|
|
|
|
ppc_md.heartbeat = NULL;
|
|
|
|
bh.p_base = CONFIG_MV64X60_NEW_BASE;
|
|
|
|
chestnut_set_bat();
|
|
|
|
#if defined(CONFIG_SERIAL_TEXT_DEBUG)
|
|
ppc_md.progress = gen550_progress;
|
|
#endif
|
|
#if defined(CONFIG_KGDB)
|
|
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
|
|
#endif
|
|
|
|
if (ppc_md.progress)
|
|
ppc_md.progress("chestnut_init(): exit", 0);
|
|
}
|