b4dcaea36b
The header files for the Pb1200/DBAu1200 boards have wrong definition for the IDE interface's decoded range length -- it should be 512 bytes according to what the IDE driver does. In addition, the IDE platform device claims 1 byte too many for its memory resource -- fix the platform code and the IDE driver in accordance. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
261 lines
7.0 KiB
C
261 lines
7.0 KiB
C
/*
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* AMD Alchemy PB1200 Referrence Board
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* Board Registers defines.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#ifndef __ASM_PB1200_H
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#define __ASM_PB1200_H
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#include <linux/types.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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// This is defined in au1000.h with bogus value
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#undef AU1X00_EXTERNAL_INT
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
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/* SPI and SMB are muxed on the Pb1200 board.
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Refer to board documentation.
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*/
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define SMBUS_PSC_BASE PSC0_BASE_ADDR
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/* AC97 and I2S are muxed on the Pb1200 board.
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Refer to board documentation.
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*/
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define I2S_PSC_BASE PSC1_BASE_ADDR
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#define BCSR_KSEG1_ADDR 0xAD800000
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typedef volatile struct
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{
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/*00*/ u16 whoami;
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u16 reserved0;
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/*04*/ u16 status;
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u16 reserved1;
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/*08*/ u16 switches;
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u16 reserved2;
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/*0C*/ u16 resets;
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u16 reserved3;
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/*10*/ u16 pcmcia;
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u16 reserved4;
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/*14*/ u16 board;
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u16 reserved5;
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/*18*/ u16 disk_leds;
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u16 reserved6;
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/*1C*/ u16 system;
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u16 reserved7;
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/*20*/ u16 intclr;
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u16 reserved8;
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/*24*/ u16 intset;
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u16 reserved9;
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/*28*/ u16 intclr_mask;
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u16 reserved10;
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/*2C*/ u16 intset_mask;
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u16 reserved11;
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/*30*/ u16 sig_status;
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u16 reserved12;
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/*34*/ u16 int_status;
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u16 reserved13;
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/*38*/ u16 reserved14;
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u16 reserved15;
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/*3C*/ u16 reserved16;
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u16 reserved17;
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} BCSR;
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static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
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/*
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* Register bit definitions for the BCSRs
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*/
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#define BCSR_WHOAMI_DCID 0x000F
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#define BCSR_WHOAMI_CPLD 0x00F0
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#define BCSR_WHOAMI_BOARD 0x0F00
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#define BCSR_STATUS_PCMCIA0VS 0x0003
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#define BCSR_STATUS_PCMCIA1VS 0x000C
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#define BCSR_STATUS_SWAPBOOT 0x0040
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#define BCSR_STATUS_FLASHBUSY 0x0100
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#define BCSR_STATUS_IDECBLID 0x0200
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#define BCSR_STATUS_SD0WP 0x0400
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#define BCSR_STATUS_SD1WP 0x0800
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#define BCSR_STATUS_U0RXD 0x1000
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#define BCSR_STATUS_U1RXD 0x2000
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#define BCSR_SWITCHES_OCTAL 0x00FF
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#define BCSR_SWITCHES_DIP_1 0x0080
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#define BCSR_SWITCHES_DIP_2 0x0040
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#define BCSR_SWITCHES_DIP_3 0x0020
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#define BCSR_SWITCHES_DIP_4 0x0010
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#define BCSR_SWITCHES_DIP_5 0x0008
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#define BCSR_SWITCHES_DIP_6 0x0004
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#define BCSR_SWITCHES_DIP_7 0x0002
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#define BCSR_SWITCHES_DIP_8 0x0001
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#define BCSR_SWITCHES_ROTARY 0x0F00
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#define BCSR_RESETS_ETH 0x0001
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#define BCSR_RESETS_CAMERA 0x0002
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#define BCSR_RESETS_DC 0x0004
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#define BCSR_RESETS_IDE 0x0008
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/* not resets but in the same register */
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#define BCSR_RESETS_WSCFSM 0x0800
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#define BCSR_RESETS_PCS0MUX 0x1000
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#define BCSR_RESETS_PCS1MUX 0x2000
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#define BCSR_RESETS_SPISEL 0x4000
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#define BCSR_RESETS_SD1MUX 0x8000
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#define BCSR_PCMCIA_PC0VPP 0x0003
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#define BCSR_PCMCIA_PC0VCC 0x000C
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#define BCSR_PCMCIA_PC0DRVEN 0x0010
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#define BCSR_PCMCIA_PC0RST 0x0080
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#define BCSR_PCMCIA_PC1VPP 0x0300
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#define BCSR_PCMCIA_PC1VCC 0x0C00
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#define BCSR_PCMCIA_PC1DRVEN 0x1000
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#define BCSR_PCMCIA_PC1RST 0x8000
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#define BCSR_BOARD_LCDVEE 0x0001
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#define BCSR_BOARD_LCDVDD 0x0002
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#define BCSR_BOARD_LCDBL 0x0004
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#define BCSR_BOARD_CAMSNAP 0x0010
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#define BCSR_BOARD_CAMPWR 0x0020
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#define BCSR_BOARD_SD0PWR 0x0040
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#define BCSR_BOARD_SD1PWR 0x0080
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#define BCSR_LEDS_DECIMALS 0x00FF
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#define BCSR_LEDS_LED0 0x0100
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#define BCSR_LEDS_LED1 0x0200
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#define BCSR_LEDS_LED2 0x0400
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#define BCSR_LEDS_LED3 0x0800
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#define BCSR_SYSTEM_VDDI 0x001F
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#define BCSR_SYSTEM_POWEROFF 0x4000
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#define BCSR_SYSTEM_RESET 0x8000
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/* Bit positions for the different interrupt sources */
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#define BCSR_INT_IDE 0x0001
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#define BCSR_INT_ETH 0x0002
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#define BCSR_INT_PC0 0x0004
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#define BCSR_INT_PC0STSCHG 0x0008
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#define BCSR_INT_PC1 0x0010
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#define BCSR_INT_PC1STSCHG 0x0020
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#define BCSR_INT_DC 0x0040
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#define BCSR_INT_FLASHBUSY 0x0080
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#define BCSR_INT_PC0INSERT 0x0100
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#define BCSR_INT_PC0EJECT 0x0200
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#define BCSR_INT_PC1INSERT 0x0400
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#define BCSR_INT_PC1EJECT 0x0800
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#define BCSR_INT_SD0INSERT 0x1000
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#define BCSR_INT_SD0EJECT 0x2000
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#define BCSR_INT_SD1INSERT 0x4000
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#define BCSR_INT_SD1EJECT 0x8000
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/* PCMCIA Db1x00 specific defines */
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
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/* VPP/VCC */
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#define SET_VCC_VPP(VCC, VPP, SLOT)\
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((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
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#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300)
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#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT
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#define AU1XXX_ATA_PHYS_ADDR (0x0C800000)
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#define AU1XXX_ATA_REG_OFFSET (5)
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#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET)
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#define AU1XXX_ATA_INT PB1200_IDE_INT
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#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
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#define AU1XXX_ATA_RQSIZE 128
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#define NAND_PHYS_ADDR 0x1C000000
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/* Timing values as described in databook, * ns value stripped of
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* lower 2 bits.
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* These defines are here rather than an SOC1200 generic file because
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* the parts chosen on another board may be different and may require
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* different timings.
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*/
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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/* Bitfield shift amounts */
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#define NAND_T_H_SHIFT 0
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#define NAND_T_PUL_SHIFT 4
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#define NAND_T_SU_SHIFT 8
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#define NAND_T_WH_SHIFT 12
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#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
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/*
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* External Interrupts for Pb1200 as of 8/6/2004.
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* Bit positions in the CPLD registers can be calculated by taking
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* the interrupt define and subtracting the PB1200_INT_BEGIN value.
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*
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* Example: IDE bis pos is = 64 - 64
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* ETH bit pos is = 65 - 64
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*/
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enum external_pb1200_ints {
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PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
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PB1200_IDE_INT = PB1200_INT_BEGIN,
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PB1200_ETH_INT,
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PB1200_PC0_INT,
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PB1200_PC0_STSCHG_INT,
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PB1200_PC1_INT,
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PB1200_PC1_STSCHG_INT,
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PB1200_DC_INT,
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PB1200_FLASHBUSY_INT,
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PB1200_PC0_INSERT_INT,
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PB1200_PC0_EJECT_INT,
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PB1200_PC1_INSERT_INT,
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PB1200_PC1_EJECT_INT,
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PB1200_SD0_INSERT_INT,
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PB1200_SD0_EJECT_INT,
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PB1200_SD1_INSERT_INT,
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PB1200_SD1_EJECT_INT,
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PB1200_INT_END = PB1200_INT_BEGIN + 15
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};
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/* For drivers/pcmcia/au1000_db1x00.c */
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#define BOARD_PC0_INT PB1200_PC0_INT
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#define BOARD_PC1_INT PB1200_PC1_INT
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#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
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/* Nand chip select */
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#define NAND_CS 1
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#endif /* __ASM_PB1200_H */
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