b95a13d79c
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
126 lines
4.4 KiB
C
126 lines
4.4 KiB
C
/*
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* arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
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*
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* Generic definitions for Marvell MV78xx0 SoC flavors:
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* MV781x0 and MV782x0.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_MV78XX0_H
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#define __ASM_ARCH_MV78XX0_H
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/*
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* Marvell MV78xx0 address maps.
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*
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* phys
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* c0000000 PCIe Memory space
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* f0800000 PCIe #0 I/O space
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* f0900000 PCIe #1 I/O space
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* f0a00000 PCIe #2 I/O space
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* f0b00000 PCIe #3 I/O space
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* f0c00000 PCIe #4 I/O space
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* f0d00000 PCIe #5 I/O space
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* f0e00000 PCIe #6 I/O space
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* f0f00000 PCIe #7 I/O space
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* f1000000 on-chip peripheral registers
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*
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* virt phys size
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* fe400000 f102x000 16K core-specific peripheral registers
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* fe700000 f0800000 1M PCIe #0 I/O space
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* fe800000 f0900000 1M PCIe #1 I/O space
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* fe900000 f0a00000 1M PCIe #2 I/O space
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* fea00000 f0b00000 1M PCIe #3 I/O space
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* feb00000 f0c00000 1M PCIe #4 I/O space
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* fec00000 f0d00000 1M PCIe #5 I/O space
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* fed00000 f0e00000 1M PCIe #6 I/O space
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* fee00000 f0f00000 1M PCIe #7 I/O space
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* fef00000 f1000000 1M on-chip peripheral registers
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*/
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#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
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#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
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#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
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#define MV78XX0_CORE_REGS_SIZE SZ_16K
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#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
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#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
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#define MV78XX0_PCIE_IO_SIZE SZ_1M
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#define MV78XX0_REGS_PHYS_BASE 0xf1000000
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#define MV78XX0_REGS_VIRT_BASE 0xfef00000
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#define MV78XX0_REGS_SIZE SZ_1M
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#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
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#define MV78XX0_PCIE_MEM_SIZE 0x30000000
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/*
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* Core-specific peripheral registers.
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*/
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#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define L2_WRITETHROUGH 0x00020000
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_ERR_OFF 0x0000
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#define IRQ_CAUSE_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0008
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#define IRQ_MASK_ERR_OFF 0x000c
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#define IRQ_MASK_LOW_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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/*
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* Register Map
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*/
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#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
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#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
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#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700)
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#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
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#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
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#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
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#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
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#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
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#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
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#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200)
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#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200)
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#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300)
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#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300)
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#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000)
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#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000)
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#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000)
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#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000)
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#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000)
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#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000)
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#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000)
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#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
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#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
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#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
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#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
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#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000)
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#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000)
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#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
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#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
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#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
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#endif
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