476f5779b7
The Freescale PCI-e controllers have an issue in that they use the PCI_PRIMARY_BUS register in the virtual P2P bridge to determine which bus number to match on when generating a type 0 config cycle. The issue is if we are renumbering bus numbers to match Linux we will try setting the PCI_PRIMARY_BUS and will not know which bus number to use for generating type 0 config cycles. We surpress writing the register in the P2P bridge and always keep it at zero. In the future when proper PCI domain support is working we should be able to remove this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
159 lines
3.8 KiB
C
159 lines
3.8 KiB
C
/*
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* Support for indirect PCI bridges.
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*
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* Copyright (C) 1998 Gabriel Paubert.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#ifdef CONFIG_PPC_INDIRECT_PCI_BE
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#define PCI_CFG_OUT out_be32
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#else
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#define PCI_CFG_OUT out_le32
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#endif
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static int
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indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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u32 bus_no, reg;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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bus_no = (bus->number == hose->first_busno) ?
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hose->self_busno : bus->number;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
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reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
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else
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reg = offset & 0xfc;
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | (bus_no << 16)
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| (devfn << 8) | reg | cfg_type));
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + (offset & 3);
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switch (len) {
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case 1:
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*val = in_8(cfg_data);
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break;
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case 2:
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*val = in_le16(cfg_data);
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break;
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default:
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*val = in_le32(cfg_data);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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u32 bus_no, reg;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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bus_no = (bus->number == hose->first_busno) ?
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hose->self_busno : bus->number;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
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reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
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else
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reg = offset & 0xfc;
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | (bus_no << 16)
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| (devfn << 8) | reg | cfg_type));
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/* surpress setting of PCI_PRIMARY_BUS */
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
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if ((offset == PCI_PRIMARY_BUS) &&
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(bus->number == hose->first_busno))
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val &= 0xffffff00;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + (offset & 3);
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switch (len) {
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case 1:
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out_8(cfg_data, val);
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break;
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case 2:
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out_le16(cfg_data, val);
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break;
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default:
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out_le32(cfg_data, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops indirect_pci_ops =
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{
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indirect_read_config,
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indirect_write_config
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};
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void __init
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setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
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void __iomem * cfg_data)
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{
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hose->cfg_addr = cfg_addr;
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hose->cfg_data = cfg_data;
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hose->ops = &indirect_pci_ops;
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}
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void __init
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setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
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{
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unsigned long base = cfg_addr & PAGE_MASK;
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void __iomem *mbase, *addr, *data;
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mbase = ioremap(base, PAGE_SIZE);
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addr = mbase + (cfg_addr & ~PAGE_MASK);
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if ((cfg_data & PAGE_MASK) != base)
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mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
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data = mbase + (cfg_data & ~PAGE_MASK);
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setup_indirect_pci_nomap(hose, addr, data);
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}
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