7117a44bc0
The system counter (sys_ctr) is a programmable system counter which provides a shared time base to the Cortex A15, A7, A53 etc cores. It is intended for use in applications where the counter is always powered on and supports multiple, unrelated clocks. The sys_ctr hardware supports: - 56-bit counter width (roll-over time greater than 40 years) - compare frame(64-bit compare value) contains programmable interrupt generation when compare value <= counter value. [dlezcano] Fixed over 80 chars length warning Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
146 lines
3.0 KiB
C
146 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2017-2019 NXP
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "timer-of.h"
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#define CMP_OFFSET 0x10000
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#define CNTCV_LO 0x8
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#define CNTCV_HI 0xc
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#define CMPCV_LO (CMP_OFFSET + 0x20)
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#define CMPCV_HI (CMP_OFFSET + 0x24)
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#define CMPCR (CMP_OFFSET + 0x2c)
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#define SYS_CTR_EN 0x1
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#define SYS_CTR_IRQ_MASK 0x2
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static void __iomem *sys_ctr_base;
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static u32 cmpcr;
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static void sysctr_timer_enable(bool enable)
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{
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writel(enable ? cmpcr | SYS_CTR_EN : cmpcr, sys_ctr_base + CMPCR);
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}
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static void sysctr_irq_acknowledge(void)
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{
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/*
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* clear the enable bit(EN =0) will clear
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* the status bit(ISTAT = 0), then the interrupt
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* signal will be negated(acknowledged).
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*/
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sysctr_timer_enable(false);
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}
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static inline u64 sysctr_read_counter(void)
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{
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u32 cnt_hi, tmp_hi, cnt_lo;
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do {
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cnt_hi = readl_relaxed(sys_ctr_base + CNTCV_HI);
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cnt_lo = readl_relaxed(sys_ctr_base + CNTCV_LO);
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tmp_hi = readl_relaxed(sys_ctr_base + CNTCV_HI);
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} while (tmp_hi != cnt_hi);
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return ((u64) cnt_hi << 32) | cnt_lo;
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}
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static int sysctr_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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u32 cmp_hi, cmp_lo;
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u64 next;
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sysctr_timer_enable(false);
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next = sysctr_read_counter();
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next += delta;
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cmp_hi = (next >> 32) & 0x00fffff;
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cmp_lo = next & 0xffffffff;
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writel_relaxed(cmp_hi, sys_ctr_base + CMPCV_HI);
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writel_relaxed(cmp_lo, sys_ctr_base + CMPCV_LO);
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sysctr_timer_enable(true);
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return 0;
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}
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static int sysctr_set_state_oneshot(struct clock_event_device *evt)
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{
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return 0;
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}
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static int sysctr_set_state_shutdown(struct clock_event_device *evt)
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{
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sysctr_timer_enable(false);
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return 0;
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}
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static irqreturn_t sysctr_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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sysctr_irq_acknowledge();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct timer_of to_sysctr = {
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.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
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.clkevt = {
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.name = "i.MX system counter timer",
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ,
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.set_state_oneshot = sysctr_set_state_oneshot,
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.set_next_event = sysctr_set_next_event,
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.set_state_shutdown = sysctr_set_state_shutdown,
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.rating = 200,
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},
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.of_irq = {
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.handler = sysctr_timer_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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.of_clk = {
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.name = "per",
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},
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};
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static void __init sysctr_clockevent_init(void)
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{
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to_sysctr.clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&to_sysctr.clkevt,
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timer_of_rate(&to_sysctr),
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0xff, 0x7fffffff);
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}
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static int __init sysctr_timer_init(struct device_node *np)
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{
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int ret = 0;
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ret = timer_of_init(np, &to_sysctr);
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if (ret)
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return ret;
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sys_ctr_base = timer_of_base(&to_sysctr);
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cmpcr = readl(sys_ctr_base + CMPCR);
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cmpcr &= ~SYS_CTR_EN;
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sysctr_clockevent_init();
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return 0;
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}
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TIMER_OF_DECLARE(sysctr_timer, "nxp,sysctr-timer", sysctr_timer_init);
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