58d0831928
The header files describe the hardware registers available in both these chips, note that most of this documentation is automatically generated from the hardware implementation.
29 lines
607 B
C
29 lines
607 B
C
#ifndef _ASM_CRIS_ARCH_ARBITER_H
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#define _ASM_CRIS_ARCH_ARBITER_H
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#define EXT_REGION 0
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#define INT_REGION 1
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typedef void (watch_callback)(void);
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enum {
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arbiter_all_dmas = 0x3ff,
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arbiter_cpu = 0xc00,
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arbiter_all_clients = 0x3fff
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};
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enum {
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arbiter_all_read = 0x55,
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arbiter_all_write = 0xaa,
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arbiter_all_accesses = 0xff
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};
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int crisv32_arbiter_allocate_bandwidth(int client, int region,
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unsigned long bandwidth);
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int crisv32_arbiter_watch(unsigned long start, unsigned long size,
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unsigned long clients, unsigned long accesses,
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watch_callback * cb);
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int crisv32_arbiter_unwatch(int id);
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#endif
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