270 lines
7.3 KiB
C
270 lines
7.3 KiB
C
/*
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* Copyright (C) 2000, 2001 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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* These are routines to set up and handle interrupts from the
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* sb1250 general purpose timer 0. We're using the timer as a
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* system clock, so we set it up to run at 100 Hz. On every
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* interrupt, we update our idea of what the time of day is,
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* then call do_timer() in the architecture-independent kernel
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* code to do general bookkeeping (e.g. update jiffies, run
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* bottom halves, etc.)
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/kernel_stat.h>
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#include <asm/irq.h>
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#include <asm/addrspace.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/sb1250_int.h>
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#include <asm/sibyte/sb1250_scd.h>
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#define IMR_IP2_VAL K_INT_MAP_I0
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#define IMR_IP3_VAL K_INT_MAP_I1
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#define IMR_IP4_VAL K_INT_MAP_I2
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#define SB1250_HPT_NUM 3
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#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
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extern int sb1250_steal_irq(int irq);
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static cycle_t sb1250_hpt_read(void);
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void __init sb1250_hpt_setup(void)
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{
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int cpu = smp_processor_id();
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if (!cpu) {
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/* Setup hpt using timer #3 but do not enable irq for it */
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__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
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__raw_writeq(SB1250_HPT_VALUE,
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IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
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__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
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IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
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mips_hpt_frequency = V_SCD_TIMER_FREQ;
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clocksource_mips.read = sb1250_hpt_read;
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clocksource_mips.mask = M_SCD_TIMER_INIT;
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}
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}
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/*
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* The general purpose timer ticks at 1 Mhz independent if
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* the rest of the system
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*/
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static void sibyte_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned int cpu = smp_processor_id();
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void __iomem *timer_cfg, *timer_init;
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timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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__raw_writeq(0, timer_cfg);
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__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
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__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
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timer_cfg);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Stop the timer until we actually program a shot */
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case CLOCK_EVT_MODE_SHUTDOWN:
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__raw_writeq(0, timer_cfg);
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break;
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case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
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;
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}
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}
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static int
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sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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unsigned int cpu = smp_processor_id();
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void __iomem *timer_cfg, *timer_init;
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timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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__raw_writeq(0, timer_cfg);
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__raw_writeq(delta, timer_init);
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__raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
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return 0;
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}
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struct clock_event_device sibyte_hpt_clockevent = {
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.name = "sb1250-counter",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = sibyte_set_mode,
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.set_next_event = sibyte_next_event,
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.shift = 32,
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.irq = 0,
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};
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static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
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{
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struct clock_event_device *cd = &sibyte_hpt_clockevent;
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct irqaction sibyte_irqaction = {
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.handler = sibyte_counter_handler,
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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.name = "timer",
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};
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/*
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* The general purpose timer ticks at 1 Mhz independent if
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* the rest of the system
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*/
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static void sibyte_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned int cpu = smp_processor_id();
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void __iomem *timer_cfg, *timer_init;
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timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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__raw_writeq(0, timer_cfg);
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__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
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__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
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timer_cfg);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Stop the timer until we actually program a shot */
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case CLOCK_EVT_MODE_SHUTDOWN:
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__raw_writeq(0, timer_cfg);
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break;
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case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
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;
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}
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}
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static int
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sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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unsigned int cpu = smp_processor_id();
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void __iomem *timer_cfg, *timer_init;
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timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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__raw_writeq(0, timer_cfg);
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__raw_writeq(delta, timer_init);
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__raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
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return 0;
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}
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struct clock_event_device sibyte_hpt_clockevent = {
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.name = "sb1250-counter",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = sibyte_set_mode,
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.set_next_event = sibyte_next_event,
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.shift = 32,
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.irq = 0,
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};
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static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
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{
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struct clock_event_device *cd = &sibyte_hpt_clockevent;
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct irqaction sibyte_irqaction = {
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.handler = sibyte_counter_handler,
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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.name = "timer",
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};
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static void __init sb1250_clockevent_init(void)
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{
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struct clock_event_device *cd = &sibyte_hpt_clockevent;
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unsigned int cpu = smp_processor_id();
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int irq = K_INT_TIMER_0 + cpu;
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/* Only have 4 general purpose timers, and we use last one as hpt */
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BUG_ON(cpu > 2);
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sb1250_mask_irq(cpu, irq);
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/* Map the timer interrupt to ip[4] of this cpu */
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__raw_writeq(IMR_IP4_VAL,
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IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
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(irq << 3)));
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cd->cpumask = cpumask_of_cpu(0);
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sb1250_unmask_irq(cpu, irq);
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sb1250_steal_irq(irq);
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/*
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* This interrupt is "special" in that it doesn't use the request_irq
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* way to hook the irq line. The timer interrupt is initialized early
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* enough to make this a major pain, and it's also firing enough to
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* warrant a bit of special case code. sb1250_timer_interrupt is
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* called directly from irq_handler.S when IP[4] is set during an
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* interrupt
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*/
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setup_irq(irq, &sibyte_irqaction);
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clockevents_register_device(cd);
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}
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void __init plat_time_init(void)
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{
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sb1250_clocksource_init();
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sb1250_clockevent_init();
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}
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/*
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* The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
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* again.
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*/
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static cycle_t sb1250_hpt_read(void)
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{
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unsigned int count;
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count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
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return SB1250_HPT_VALUE - count;
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}
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