84e250ffa7
Let the otg_transceiver in MUSB be managed by an external driver; don't assume it's integrated. OMAP3 chips need it to be external, and there may be ways to interact with the transceiver which add functionality to the system. Platform init code is responsible for setting up the transeciver, probably using the NOP transceiver for integrated transceivers. External ones will use whatever the board init code provided, such as twl4030 or something more hands-off. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
476 lines
13 KiB
C
476 lines
13 KiB
C
/*
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <mach/memory.h>
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#include <mach/gpio.h>
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#include <asm/mach-types.h>
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#include "musb_core.h"
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#ifdef CONFIG_MACH_DAVINCI_EVM
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#define GPIO_nVBUS_DRV 87
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#endif
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#include "davinci.h"
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#include "cppi_dma.h"
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#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
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#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
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/* REVISIT (PM) we should be able to keep the PHY in low power mode most
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* of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
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* and, when in host mode, autosuspending idle root ports... PHYPLLON
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* (overriding SUSPENDM?) then likely needs to stay off.
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*/
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static inline void phy_on(void)
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{
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u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
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/* power everything up; start the on-chip PHY and its PLL */
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phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
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phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
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__raw_writel(phy_ctrl, USB_PHY_CTRL);
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/* wait for PLL to lock before proceeding */
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while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
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cpu_relax();
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}
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static inline void phy_off(void)
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{
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u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
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/* powerdown the on-chip PHY, its PLL, and the OTG block */
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phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
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phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
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__raw_writel(phy_ctrl, USB_PHY_CTRL);
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}
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static int dma_off = 1;
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void musb_platform_enable(struct musb *musb)
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{
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u32 tmp, old, val;
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/* workaround: setup irqs through both register sets */
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tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
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<< DAVINCI_USB_TXINT_SHIFT;
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
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old = tmp;
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tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
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<< DAVINCI_USB_RXINT_SHIFT;
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
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tmp |= old;
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val = ~MUSB_INTR_SOF;
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tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
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if (is_dma_capable() && !dma_off)
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printk(KERN_WARNING "%s %s: dma not reactivated\n",
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__FILE__, __func__);
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else
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dma_off = 0;
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/* force a DRVVBUS irq so we can start polling for ID change */
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if (is_otg_enabled(musb))
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
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DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
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}
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/*
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* Disable the HDRC and flush interrupts
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*/
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void musb_platform_disable(struct musb *musb)
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{
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/* because we don't set CTRLR.UINT, "important" to:
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* - not read/write INTRUSB/INTRUSBE
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* - (except during initial setup, as workaround)
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* - use INTSETR/INTCLRR instead
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*/
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
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DAVINCI_USB_USBINT_MASK
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| DAVINCI_USB_TXINT_MASK
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| DAVINCI_USB_RXINT_MASK);
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
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if (is_dma_capable() && !dma_off)
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WARNING("dma still active\n");
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}
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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#define portstate(stmt) stmt
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#else
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#define portstate(stmt)
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#endif
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/*
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* VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
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* which doesn't wire DRVVBUS to the FET that switches it. Unclear
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* if that's a problem with the DM6446 chip or just with that board.
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*
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* In either case, the DM355 EVM automates DRVVBUS the normal way,
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* when J10 is out, and TI documents it as handling OTG.
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*/
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#ifdef CONFIG_MACH_DAVINCI_EVM
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static int vbus_state = -1;
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/* I2C operations are always synchronous, and require a task context.
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* With unloaded systems, using the shared workqueue seems to suffice
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* to satisfy the 100msec A_WAIT_VRISE timeout...
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*/
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static void evm_deferred_drvvbus(struct work_struct *ignored)
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{
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gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
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vbus_state = !vbus_state;
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}
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#endif /* EVM */
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static void davinci_source_power(struct musb *musb, int is_on, int immediate)
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{
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#ifdef CONFIG_MACH_DAVINCI_EVM
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if (is_on)
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is_on = 1;
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if (vbus_state == is_on)
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return;
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vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
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if (machine_is_davinci_evm()) {
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static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
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if (immediate)
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gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
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else
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schedule_work(&evm_vbus_work);
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}
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if (immediate)
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vbus_state = is_on;
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#endif
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}
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static void davinci_set_vbus(struct musb *musb, int is_on)
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{
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WARN_ON(is_on && is_peripheral_active(musb));
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davinci_source_power(musb, is_on, 0);
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}
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#define POLL_SECONDS 2
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static struct timer_list otg_workaround;
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static void otg_timer(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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void __iomem *mregs = musb->mregs;
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u8 devctl;
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unsigned long flags;
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/* We poll because DaVinci's won't expose several OTG-critical
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* status change events (from the transceiver) otherwise.
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*/
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->state) {
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case OTG_STATE_A_WAIT_VFALL:
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/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
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* seems to mis-handle session "start" otherwise (or in our
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* case "recover"), in routine "VBUS was valid by the time
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* VBUSERR got reported during enumeration" cases.
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*/
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if (devctl & MUSB_DEVCTL_VBUS) {
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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break;
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}
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musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
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MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
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break;
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case OTG_STATE_B_IDLE:
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if (!is_peripheral_enabled(musb))
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break;
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/* There's no ID-changed IRQ, so we have no good way to tell
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* when to switch to the A-Default state machine (by setting
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* the DEVCTL.SESSION flag).
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*
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* Workaround: whenever we're in B_IDLE, try setting the
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* session flag every few seconds. If it works, ID was
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* grounded and we're now in the A-Default state machine.
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*
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* NOTE setting the session flag is _supposed_ to trigger
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* SRP, but clearly it doesn't.
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*/
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musb_writeb(mregs, MUSB_DEVCTL,
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devctl | MUSB_DEVCTL_SESSION);
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE)
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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else
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musb->xceiv->state = OTG_STATE_A_IDLE;
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break;
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default:
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static irqreturn_t davinci_interrupt(int irq, void *__hci)
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{
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unsigned long flags;
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irqreturn_t retval = IRQ_NONE;
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struct musb *musb = __hci;
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void __iomem *tibase = musb->ctrl_base;
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struct cppi *cppi;
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u32 tmp;
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spin_lock_irqsave(&musb->lock, flags);
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/* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
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* the Mentor registers (except for setup), use the TI ones and EOI.
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*
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* Docs describe irq "vector" registers asociated with the CPPI and
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* USB EOI registers. These hold a bitmask corresponding to the
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* current IRQ, not an irq handler address. Would using those bits
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* resolve some of the races observed in this dispatch code??
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*/
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/* CPPI interrupts share the same IRQ line, but have their own
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* mask, state, "vector", and EOI registers.
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*/
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cppi = container_of(musb->dma_controller, struct cppi, controller);
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if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
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retval = cppi_interrupt(irq, __hci);
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/* ack and handle non-CPPI interrupts */
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tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
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musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
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DBG(4, "IRQ %08x\n", tmp);
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musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
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>> DAVINCI_USB_RXINT_SHIFT;
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musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
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>> DAVINCI_USB_TXINT_SHIFT;
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musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
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>> DAVINCI_USB_USBINT_SHIFT;
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/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
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* DaVinci's missing ID change IRQ. We need an ID change IRQ to
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* switch appropriately between halves of the OTG state machine.
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* Managing DEVCTL.SESSION per Mentor docs requires we know its
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* value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
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* Also, DRVVBUS pulses for SRP (but not at 5V) ...
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*/
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if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
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int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
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void __iomem *mregs = musb->mregs;
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u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
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int err = musb->int_usb & MUSB_INTR_VBUSERROR;
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err = is_host_enabled(musb)
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&& (musb->int_usb & MUSB_INTR_VBUSERROR);
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if (err) {
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/* The Mentor core doesn't debounce VBUS as needed
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* to cope with device connect current spikes. This
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* means it's not uncommon for bus-powered devices
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* to get VBUS errors during enumeration.
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*
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* This is a workaround, but newer RTL from Mentor
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* seems to allow a better one: "re"starting sessions
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* without waiting (on EVM, a **long** time) for VBUS
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* to stop registering in devctl.
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*/
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musb->int_usb &= ~MUSB_INTR_VBUSERROR;
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musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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WARNING("VBUS error workaround (delay coming)\n");
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} else if (is_host_enabled(musb) && drvvbus) {
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musb->is_active = 1;
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MUSB_HST_MODE(musb);
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musb->xceiv->default_a = 1;
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musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
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portstate(musb->port1_status |= USB_PORT_STAT_POWER);
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del_timer(&otg_workaround);
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} else {
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musb->is_active = 0;
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MUSB_DEV_MODE(musb);
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musb->xceiv->default_a = 0;
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musb->xceiv->state = OTG_STATE_B_IDLE;
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portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
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}
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/* NOTE: this must complete poweron within 100 msec */
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davinci_source_power(musb, drvvbus, 0);
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DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
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drvvbus ? "on" : "off",
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otg_state_string(musb),
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err ? " ERROR" : "",
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devctl);
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retval = IRQ_HANDLED;
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}
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if (musb->int_tx || musb->int_rx || musb->int_usb)
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retval |= musb_interrupt(musb);
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/* irq stays asserted until EOI is written */
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musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
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/* poll for ID change */
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if (is_otg_enabled(musb)
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&& musb->xceiv->state == OTG_STATE_B_IDLE)
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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spin_unlock_irqrestore(&musb->lock, flags);
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return retval;
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}
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int musb_platform_set_mode(struct musb *musb, u8 mode)
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{
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/* EVM can't do this (right?) */
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return -EIO;
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}
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int __init musb_platform_init(struct musb *musb)
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{
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void __iomem *tibase = musb->ctrl_base;
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u32 revision;
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usb_nop_xceiv_register();
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musb->xceiv = otg_get_transceiver();
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if (!musb->xceiv)
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return -ENODEV;
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musb->mregs += DAVINCI_BASE_OFFSET;
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clk_enable(musb->clock);
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/* returns zero if e.g. not clocked */
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revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
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if (revision == 0)
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goto fail;
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if (is_host_enabled(musb))
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setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
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musb->board_set_vbus = davinci_set_vbus;
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davinci_source_power(musb, 0, 1);
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/* dm355 EVM swaps D+/D- for signal integrity, and
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* is clocked from the main 24 MHz crystal.
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*/
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if (machine_is_davinci_dm355_evm()) {
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u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
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phy_ctrl &= ~(3 << 9);
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phy_ctrl |= USBPHY_DATAPOL;
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__raw_writel(phy_ctrl, USB_PHY_CTRL);
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}
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/* reset the controller */
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musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
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/* start the on-chip PHY and its PLL */
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phy_on();
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msleep(5);
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/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
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pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
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revision, __raw_readl(USB_PHY_CTRL),
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musb_readb(tibase, DAVINCI_USB_CTRL_REG));
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musb->isr = davinci_interrupt;
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return 0;
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fail:
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usb_nop_xceiv_unregister();
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return -ENODEV;
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}
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int musb_platform_exit(struct musb *musb)
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{
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if (is_host_enabled(musb))
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del_timer_sync(&otg_workaround);
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davinci_source_power(musb, 0 /*off*/, 1);
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/* delay, to avoid problems with module reload */
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if (is_host_enabled(musb) && musb->xceiv->default_a) {
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int maxdelay = 30;
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u8 devctl, warn = 0;
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/* if there's no peripheral connected, this can take a
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* long time to fall, especially on EVM with huge C133.
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*/
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do {
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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if (!(devctl & MUSB_DEVCTL_VBUS))
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break;
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if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
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warn = devctl & MUSB_DEVCTL_VBUS;
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DBG(1, "VBUS %d\n",
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warn >> MUSB_DEVCTL_VBUS_SHIFT);
|
|
}
|
|
msleep(1000);
|
|
maxdelay--;
|
|
} while (maxdelay > 0);
|
|
|
|
/* in OTG mode, another host might be connected */
|
|
if (devctl & MUSB_DEVCTL_VBUS)
|
|
DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
|
|
}
|
|
|
|
phy_off();
|
|
|
|
clk_disable(musb->clock);
|
|
|
|
usb_nop_xceiv_unregister();
|
|
|
|
return 0;
|
|
}
|