556dcee7b8
Change all users of header files to correct path. Remove some unneeded headers for arch-v32. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
169 lines
5.3 KiB
C
169 lines
5.3 KiB
C
/*
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* Set up paging and the MMU.
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*
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* Copyright (C) 2000-2003, Axis Communications AB.
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*
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* Authors: Bjorn Wesen <bjornw@axis.com>
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* Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
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*/
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#include <linux/mmzone.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <arch/hwregs/asm/mmu_defs_asm.h>
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#include <arch/hwregs/supp_reg.h>
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extern void tlb_init(void);
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/*
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* The kernel is already mapped with linear mapping at kseg_c so there's no
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* need to map it with a page table. However, head.S also temporarily mapped it
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* at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various
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* other paging stuff.
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*/
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void __init
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cris_mmu_init(void)
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{
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unsigned long mmu_config;
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unsigned long mmu_kbase_hi;
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unsigned long mmu_kbase_lo;
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unsigned short mmu_page_id;
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/*
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* Make sure the current pgd table points to something sane, even if it
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* is most probably not used until the next switch_mm.
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*/
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per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
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#ifdef CONFIG_SMP
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{
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pgd_t **pgd;
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pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
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SUPP_BANK_SEL(1);
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SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
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SUPP_BANK_SEL(2);
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SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
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}
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#endif
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/* Initialise the TLB. Function found in tlb.c. */
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tlb_init();
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/* Enable exceptions and initialize the kernel segments. */
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mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on) |
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REG_STATE(mmu, rw_mm_cfg, acc, on) |
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REG_STATE(mmu, rw_mm_cfg, ex, on) |
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REG_STATE(mmu, rw_mm_cfg, inv, on) |
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REG_STATE(mmu, rw_mm_cfg, seg_f, linear) |
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REG_STATE(mmu, rw_mm_cfg, seg_e, linear) |
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REG_STATE(mmu, rw_mm_cfg, seg_d, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
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REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
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#ifndef CONFIG_ETRAX_VCS_SIM
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REG_STATE(mmu, rw_mm_cfg, seg_a, page) |
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#else
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REG_STATE(mmu, rw_mm_cfg, seg_a, linear) |
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#endif
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REG_STATE(mmu, rw_mm_cfg, seg_9, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_8, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_7, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_6, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_5, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_4, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_3, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_2, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_1, page) |
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REG_STATE(mmu, rw_mm_cfg, seg_0, page));
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mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
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REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
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REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
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#ifndef CONFIG_ETRAX_VCS_SIM
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REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) |
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#else
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REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa) |
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#endif
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REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0));
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mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) |
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REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0));
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mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0);
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/* Update the instruction MMU. */
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SUPP_BANK_SEL(BANK_IM);
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SUPP_REG_WR(RW_MM_CFG, mmu_config);
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SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
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SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
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SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
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/* Update the data MMU. */
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SUPP_BANK_SEL(BANK_DM);
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SUPP_REG_WR(RW_MM_CFG, mmu_config);
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SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
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SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
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SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
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SPEC_REG_WR(SPEC_REG_PID, 0);
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/*
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* The MMU has been enabled ever since head.S but just to make it
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* totally obvious enable it here as well.
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*/
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SUPP_BANK_SEL(BANK_GC);
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SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */
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}
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void __init
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paging_init(void)
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{
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int i;
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unsigned long zones_size[MAX_NR_ZONES];
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printk("Setting up paging and the MMU.\n");
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/* Clear out the init_mm.pgd that will contain the kernel's mappings. */
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for(i = 0; i < PTRS_PER_PGD; i++)
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swapper_pg_dir[i] = __pgd(0);
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cris_mmu_init();
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/*
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* Initialize the bad page table and bad page to point to a couple of
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* allocated pages.
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*/
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empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
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memset((void *) empty_zero_page, 0, PAGE_SIZE);
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/* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */
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zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
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for (i = 1; i < MAX_NR_ZONES; i++)
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zones_size[i] = 0;
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/*
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* Use free_area_init_node instead of free_area_init, because it is
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* designed for systems where the DRAM starts at an address
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* substantially higher than 0, like us (we start at PAGE_OFFSET). This
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* saves space in the mem_map page array.
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*/
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free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
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mem_map = contig_page_data.node_mem_map;
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}
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