89d63fe179
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
205 lines
6.3 KiB
C
205 lines
6.3 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
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*
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* Define the pci_ops for TX3927.
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*
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* Much of the code is derived from the original DDB5074 port by
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* Geert Uytterhoeven <geert@sonycom.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/addrspace.h>
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#include <asm/txx9/tx3927.h>
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static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
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unsigned char where)
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{
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if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
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return PCIBIOS_DEVICE_NOT_FOUND;
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tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) |
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((dev_fn & 0xff) << 0x08) |
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(where & 0xfc);
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/* clear M_ABORT and Disable M_ABORT Int. */
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
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tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
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return PCIBIOS_SUCCESSFUL;
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}
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static inline int check_abort(void)
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{
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if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
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tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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int ret;
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ret = mkaddr(bus->number, devfn, where);
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if (ret)
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return ret;
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switch (size) {
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case 1:
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*val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
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break;
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case 2:
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*val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
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break;
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case 4:
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*val = le32_to_cpu(tx3927_pcicptr->icd);
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break;
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}
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return check_abort();
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}
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static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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int ret;
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ret = mkaddr(bus->number, devfn, where);
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if (ret)
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return ret;
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switch (size) {
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case 1:
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*(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
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break;
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case 2:
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*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
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cpu_to_le16(val);
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break;
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case 4:
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tx3927_pcicptr->icd = cpu_to_le32(val);
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}
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if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
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tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
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return PCIBIOS_DEVICE_NOT_FOUND;
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return check_abort();
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}
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static struct pci_ops tx3927_pci_ops = {
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.read = tx3927_pci_read_config,
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.write = tx3927_pci_write_config,
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};
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void __init tx3927_pcic_setup(struct pci_controller *channel,
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unsigned long sdram_size, int extarb)
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{
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unsigned long flags;
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unsigned long io_base =
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channel->io_resource->start + mips_io_port_base - IO_BASE;
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unsigned long io_size =
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channel->io_resource->end - channel->io_resource->start;
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unsigned long io_pciaddr =
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channel->io_resource->start - channel->io_offset;
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unsigned long mem_base =
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channel->mem_resource->start;
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unsigned long mem_size =
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channel->mem_resource->end - channel->mem_resource->start;
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unsigned long mem_pciaddr =
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channel->mem_resource->start - channel->mem_offset;
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printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
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tx3927_pcicptr->did, tx3927_pcicptr->vid,
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tx3927_pcicptr->rid,
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extarb ? "External" : "Internal");
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channel->pci_ops = &tx3927_pci_ops;
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local_irq_save(flags);
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/* Disable External PCI Config. Access */
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tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
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#ifdef __BIG_ENDIAN
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tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
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TX3927_PCIC_LBC_TIBSE |
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TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
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#endif
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/* LB->PCI mappings */
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tx3927_pcicptr->iomas = ~(io_size - 1);
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tx3927_pcicptr->ilbioma = io_base;
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tx3927_pcicptr->ipbioma = io_pciaddr;
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tx3927_pcicptr->mmas = ~(mem_size - 1);
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tx3927_pcicptr->ilbmma = mem_base;
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tx3927_pcicptr->ipbmma = mem_pciaddr;
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/* PCI->LB mappings */
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tx3927_pcicptr->iobas = 0xffffffff;
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tx3927_pcicptr->ioba = 0;
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tx3927_pcicptr->tlbioma = 0;
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tx3927_pcicptr->mbas = ~(sdram_size - 1);
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tx3927_pcicptr->mba = 0;
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tx3927_pcicptr->tlbmma = 0;
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/* Enable Direct mapping Address Space Decoder */
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tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
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/* Clear All Local Bus Status */
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tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
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/* Enable All Local Bus Interrupts */
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tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
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/* Clear All PCI Status Error */
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tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
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/* Enable All PCI Status Error Interrupts */
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tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
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/* PCIC Int => IRC IRQ10 */
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tx3927_pcicptr->il = TX3927_IR_PCI;
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/* Target Control (per errata) */
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tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
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/* Enable Bus Arbiter */
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if (!extarb)
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tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
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tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_IO |
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
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local_irq_restore(flags);
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}
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