7a8fc9b248
This patch lets the files using linux/version.h match the files that #include it. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
260 lines
7.9 KiB
C
260 lines
7.9 KiB
C
/*
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* Copyright (c) Intel Corp. 2007.
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* All Rights Reserved.
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*
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* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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* develop this driver.
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*
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* This file is part of the Vermilion Range fb driver.
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* The Vermilion Range fb driver is free software;
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* you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The Vermilion Range fb driver is distributed
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* in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this driver; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Authors:
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* Thomas Hellström <thomas-at-tungstengraphics-dot-com>
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*/
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#ifndef _VERMILION_H_
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#define _VERMILION_H_
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <asm/atomic.h>
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#include <linux/mutex.h>
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#define VML_DEVICE_GPU 0x5002
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#define VML_DEVICE_VDC 0x5009
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#define VML_VRAM_AREAS 3
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#define VML_MAX_XRES 1024
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#define VML_MAX_YRES 768
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#define VML_MAX_XRES_VIRTUAL 1040
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/*
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* Display controller registers:
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*/
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/* Display controller 10-bit color representation */
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#define VML_R_MASK 0x3FF00000
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#define VML_R_SHIFT 20
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#define VML_G_MASK 0x000FFC00
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#define VML_G_SHIFT 10
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#define VML_B_MASK 0x000003FF
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#define VML_B_SHIFT 0
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/* Graphics plane control */
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#define VML_DSPCCNTR 0x00072180
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#define VML_GFX_ENABLE 0x80000000
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#define VML_GFX_GAMMABYPASS 0x40000000
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#define VML_GFX_ARGB1555 0x0C000000
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#define VML_GFX_RGB0888 0x18000000
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#define VML_GFX_ARGB8888 0x1C000000
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#define VML_GFX_ALPHACONST 0x02000000
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#define VML_GFX_ALPHAMULT 0x01000000
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#define VML_GFX_CONST_ALPHA 0x000000FF
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/* Graphics plane start address. Pixel aligned. */
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#define VML_DSPCADDR 0x00072184
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/* Graphics plane stride register. */
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#define VML_DSPCSTRIDE 0x00072188
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/* Graphics plane position register. */
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#define VML_DSPCPOS 0x0007218C
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#define VML_POS_YMASK 0x0FFF0000
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#define VML_POS_YSHIFT 16
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#define VML_POS_XMASK 0x00000FFF
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#define VML_POS_XSHIFT 0
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/* Graphics plane height and width */
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#define VML_DSPCSIZE 0x00072190
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#define VML_SIZE_HMASK 0x0FFF0000
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#define VML_SIZE_HSHIFT 16
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#define VML_SISE_WMASK 0x00000FFF
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#define VML_SIZE_WSHIFT 0
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/* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
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#define VML_DSPCGAMLUT 0x00072200
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/* Pixel video output configuration register */
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#define VML_PVOCONFIG 0x00061140
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#define VML_CONFIG_BASE 0x80000000
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#define VML_CONFIG_PIXEL_SWAP 0x04000000
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#define VML_CONFIG_DE_INV 0x01000000
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#define VML_CONFIG_HREF_INV 0x00400000
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#define VML_CONFIG_VREF_INV 0x00100000
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#define VML_CONFIG_CLK_INV 0x00040000
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#define VML_CONFIG_CLK_DIV2 0x00010000
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#define VML_CONFIG_ESTRB_INV 0x00008000
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/* Pipe A Horizontal total register */
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#define VML_HTOTAL_A 0x00060000
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#define VML_HTOTAL_MASK 0x1FFF0000
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#define VML_HTOTAL_SHIFT 16
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#define VML_HTOTAL_VAL 8192
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#define VML_HACTIVE_MASK 0x000007FF
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#define VML_HACTIVE_SHIFT 0
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#define VML_HACTIVE_VAL 4096
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/* Pipe A Horizontal Blank register */
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#define VML_HBLANK_A 0x00060004
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#define VML_HBLANK_END_MASK 0x1FFF0000
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#define VML_HBLANK_END_SHIFT 16
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#define VML_HBLANK_END_VAL 8192
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#define VML_HBLANK_START_MASK 0x00001FFF
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#define VML_HBLANK_START_SHIFT 0
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#define VML_HBLANK_START_VAL 8192
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/* Pipe A Horizontal Sync register */
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#define VML_HSYNC_A 0x00060008
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#define VML_HSYNC_END_MASK 0x1FFF0000
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#define VML_HSYNC_END_SHIFT 16
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#define VML_HSYNC_END_VAL 8192
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#define VML_HSYNC_START_MASK 0x00001FFF
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#define VML_HSYNC_START_SHIFT 0
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#define VML_HSYNC_START_VAL 8192
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/* Pipe A Vertical total register */
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#define VML_VTOTAL_A 0x0006000C
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#define VML_VTOTAL_MASK 0x1FFF0000
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#define VML_VTOTAL_SHIFT 16
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#define VML_VTOTAL_VAL 8192
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#define VML_VACTIVE_MASK 0x000007FF
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#define VML_VACTIVE_SHIFT 0
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#define VML_VACTIVE_VAL 4096
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/* Pipe A Vertical Blank register */
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#define VML_VBLANK_A 0x00060010
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#define VML_VBLANK_END_MASK 0x1FFF0000
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#define VML_VBLANK_END_SHIFT 16
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#define VML_VBLANK_END_VAL 8192
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#define VML_VBLANK_START_MASK 0x00001FFF
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#define VML_VBLANK_START_SHIFT 0
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#define VML_VBLANK_START_VAL 8192
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/* Pipe A Vertical Sync register */
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#define VML_VSYNC_A 0x00060014
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#define VML_VSYNC_END_MASK 0x1FFF0000
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#define VML_VSYNC_END_SHIFT 16
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#define VML_VSYNC_END_VAL 8192
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#define VML_VSYNC_START_MASK 0x00001FFF
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#define VML_VSYNC_START_SHIFT 0
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#define VML_VSYNC_START_VAL 8192
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/* Pipe A Source Image size (minus one - equal to active size)
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* Programmable while pipe is enabled.
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*/
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#define VML_PIPEASRC 0x0006001C
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#define VML_PIPEASRC_HMASK 0x0FFF0000
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#define VML_PIPEASRC_HSHIFT 16
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#define VML_PIPEASRC_VMASK 0x00000FFF
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#define VML_PIPEASRC_VSHIFT 0
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/* Pipe A Border Color Pattern register (10 bit color) */
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#define VML_BCLRPAT_A 0x00060020
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/* Pipe A Canvas Color register (10 bit color) */
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#define VML_CANVSCLR_A 0x00060024
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/* Pipe A Configuration register */
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#define VML_PIPEACONF 0x00070008
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#define VML_PIPE_BASE 0x00000000
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#define VML_PIPE_ENABLE 0x80000000
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#define VML_PIPE_FORCE_BORDER 0x02000000
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#define VML_PIPE_PLANES_OFF 0x00080000
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#define VML_PIPE_ARGB_OUTPUT_MODE 0x00040000
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/* Pipe A FIFO setting */
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#define VML_DSPARB 0x00070030
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#define VML_FIFO_DEFAULT 0x00001D9C
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/* MDVO rcomp status & pads control register */
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#define VML_RCOMPSTAT 0x00070048
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#define VML_MDVO_VDC_I_RCOMP 0x80000000
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#define VML_MDVO_POWERSAVE_OFF 0x00000008
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#define VML_MDVO_PAD_ENABLE 0x00000004
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#define VML_MDVO_PULLDOWN_ENABLE 0x00000001
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struct vml_par {
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struct pci_dev *vdc;
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u64 vdc_mem_base;
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u64 vdc_mem_size;
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char __iomem *vdc_mem;
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struct pci_dev *gpu;
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u64 gpu_mem_base;
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u64 gpu_mem_size;
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char __iomem *gpu_mem;
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atomic_t refcount;
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};
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struct vram_area {
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unsigned long logical;
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unsigned long phys;
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unsigned long size;
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unsigned order;
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};
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struct vml_info {
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struct fb_info info;
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struct vml_par *par;
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struct list_head head;
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struct vram_area vram[VML_VRAM_AREAS];
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u64 vram_start;
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u64 vram_contig_size;
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u32 num_areas;
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void __iomem *vram_logical;
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u32 pseudo_palette[16];
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u32 stride;
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u32 bytes_per_pixel;
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atomic_t vmas;
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int cur_blank_mode;
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int pipe_disabled;
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};
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/*
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* Subsystem
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*/
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struct vml_sys {
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char *name;
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/*
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* Save / Restore;
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*/
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int (*save) (struct vml_sys * sys);
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int (*restore) (struct vml_sys * sys);
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/*
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* PLL programming;
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*/
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int (*set_clock) (struct vml_sys * sys, int clock);
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int (*nearest_clock) (const struct vml_sys * sys, int clock);
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};
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extern int vmlfb_register_subsys(struct vml_sys *sys);
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extern void vmlfb_unregister_subsys(struct vml_sys *sys);
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#define VML_READ32(_par, _offset) \
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(ioread32((_par)->vdc_mem + (_offset)))
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#define VML_WRITE32(_par, _offset, _value) \
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iowrite32(_value, (_par)->vdc_mem + (_offset))
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#endif
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