e868d61272
Spelling fixes in arch/sh/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* Definitions for the ST40 PCI hardware.
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*/
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#ifndef __PCI_ST40_H__
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#define __PCI_ST40_H__
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#define ST40PCI_VCR_STATUS 0x00
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#define ST40PCI_VCR_VERSION 0x08
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#define ST40PCI_CR 0x10
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#define CR_SOFT_RESET (1<<12)
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#define CR_PFCS (1<<11)
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#define CR_PFE (1<<9)
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#define CR_BMAM (1<<6)
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#define CR_HOST (1<<5)
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#define CR_CLKEN (1<<4)
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#define CR_SOCS (1<<3)
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#define CR_IOCS (1<<2)
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#define CR_RSTCTL (1<<1)
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#define CR_CFINT (1<<0)
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#define CR_LOCK_MASK 0x5a000000
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#define ST40PCI_LSR0 0X14
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#define ST40PCI_LAR0 0x1c
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#define ST40PCI_INT 0x24
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#define INT_MNLTDIM (1<<15)
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#define INT_TTADI (1<<14)
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#define INT_TMTO (1<<9)
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#define INT_MDEI (1<<8)
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#define INT_APEDI (1<<7)
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#define INT_SDI (1<<6)
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#define INT_DPEITW (1<<5)
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#define INT_PEDITR (1<<4)
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#define INT_TADIM (1<<3)
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#define INT_MADIM (1<<2)
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#define INT_MWPDI (1<<1)
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#define INT_MRDPEI (1<<0)
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#define ST40PCI_INTM 0x28
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#define ST40PCI_AIR 0x2c
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#define ST40PCI_CIR 0x30
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#define CIR_PIOTEM (1<<31)
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#define CIR_RWTET (1<<26)
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#define ST40PCI_AINT 0x40
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#define AINT_MBI (1<<13)
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#define AINT_TBTOI (1<<12)
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#define AINT_MBTOI (1<<11)
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#define AINT_TAI (1<<3)
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#define AINT_MAI (1<<2)
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#define AINT_RDPEI (1<<1)
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#define AINT_WDPE (1<<0)
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#define ST40PCI_AINTM 0x44
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#define ST40PCI_BMIR 0x48
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#define ST40PCI_PAR 0x4c
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#define ST40PCI_MBR 0x50
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#define ST40PCI_IOBR 0x54
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#define ST40PCI_PINT 0x58
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#define ST40PCI_PINTM 0x5c
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#define ST40PCI_MBMR 0x70
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#define ST40PCI_IOBMR 0x74
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#define ST40PCI_PDR 0x78
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/* H8 specific registers start here */
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#define ST40PCI_WCBAR 0x7c
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#define ST40PCI_LOCCFG_UNLOCK 0x34
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#define ST40PCI_RBAR0 0x100
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#define ST40PCI_RSR0 0x104
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#define ST40PCI_RLAR0 0x108
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#define ST40PCI_RBAR1 0x110
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#define ST40PCI_RSR1 0x114
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#define ST40PCI_RLAR1 0x118
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#define ST40PCI_RBAR2 0x120
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#define ST40PCI_RSR2 0x124
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#define ST40PCI_RLAR2 0x128
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#define ST40PCI_RBAR3 0x130
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#define ST40PCI_RSR3 0x134
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#define ST40PCI_RLAR3 0x138
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#define ST40PCI_RBAR4 0x140
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#define ST40PCI_RSR4 0x144
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#define ST40PCI_RLAR4 0x148
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#define ST40PCI_RBAR5 0x150
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#define ST40PCI_RSR5 0x154
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#define ST40PCI_RLAR5 0x158
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#define ST40PCI_RBAR6 0x160
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#define ST40PCI_RSR6 0x164
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#define ST40PCI_RLAR6 0x168
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#define ST40PCI_RBAR7 0x170
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#define ST40PCI_RSR7 0x174
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#define ST40PCI_RLAR7 0x178
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#define ST40PCI_RBAR(n) (0x100+(0x10*(n)))
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#define ST40PCI_RSR(n) (0x104+(0x10*(n)))
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#define ST40PCI_RLAR(n) (0x108+(0x10*(n)))
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#define ST40PCI_PERF 0x80
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#define PERF_MASTER_WRITE_POSTING (1<<4)
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/* H8 specific registers end here */
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/* These are configs space registers */
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#define ST40PCI_CSR_VID 0x10000
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#define ST40PCI_CSR_DID 0x10002
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#define ST40PCI_CSR_CMD 0x10004
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#define ST40PCI_CSR_STATUS 0x10006
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#define ST40PCI_CSR_MBAR0 0x10010
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#define ST40PCI_CSR_TRDY 0x10040
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#define ST40PCI_CSR_RETRY 0x10041
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#define ST40PCI_CSR_MIT 0x1000d
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#define ST40_IO_ADDR 0xb6000000
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#endif /* __PCI_ST40_H__ */
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