40d4857534
If the sn2_rtc clock is present then it is a must have since sn2_rtc provides a synchronized time source on Altix systems. So elevate the priority to 450. Otherwise the ITC would take precendence. Altix systems currently do not boot because the ITC clocksource is broken. It seems to assume that ITCs are synchronized and as a result nanosleep hangs (may be fixed in a different patch). While we are at it: Remove the sn2_mc definition. The sn2_rtc has a fixed address. No point in reading the address from memory. Removing it avoids touching one cacheline. Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* linux/arch/ia64/sn/kernel/sn2/timer.c
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*
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* Copyright (C) 2003 Silicon Graphics, Inc.
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* Copyright (C) 2003 Hewlett-Packard Co
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* David Mosberger <davidm@hpl.hp.com>: updated for new timer-interpolation infrastructure
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/clocksource.h>
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#include <asm/hw_irq.h>
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#include <asm/system.h>
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#include <asm/timex.h>
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#include <asm/sn/leds.h>
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#include <asm/sn/shub_mmr.h>
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#include <asm/sn/clksupport.h>
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extern unsigned long sn_rtc_cycles_per_second;
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static cycle_t read_sn2(void)
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{
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return (cycle_t)readq(RTC_COUNTER_ADDR);
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}
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static struct clocksource clocksource_sn2 = {
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.name = "sn2_rtc",
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.rating = 450,
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.read = read_sn2,
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.mask = (1LL << 55) - 1,
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.mult = 0,
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* sn udelay uses the RTC instead of the ITC because the ITC is not
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* synchronized across all CPUs, and the thread may migrate to another CPU
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* if preemption is enabled.
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*/
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static void
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ia64_sn_udelay (unsigned long usecs)
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{
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unsigned long start = rtc_time();
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unsigned long end = start +
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usecs * sn_rtc_cycles_per_second / 1000000;
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while (time_before((unsigned long)rtc_time(), end))
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cpu_relax();
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}
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void __init sn_timer_init(void)
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{
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clocksource_sn2.fsys_mmio = RTC_COUNTER_ADDR;
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clocksource_sn2.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
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clocksource_sn2.shift);
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clocksource_register(&clocksource_sn2);
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ia64_udelay = &ia64_sn_udelay;
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}
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