1a442fe02d
This adds basic support for SH-X3 SMP (4 CPUs). More IPI and cache debugging is necessary, mostly interfacing the d-cache coherency and the I-cache broadcast invalidates. Only for testing at present! Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
121 lines
2.7 KiB
C
121 lines
2.7 KiB
C
/*
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* SH-X3 SMP
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*
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* Copyright (C) 2007 Paul Mundt
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* Copyright (C) 2007 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/cpumask.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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void __init plat_smp_setup(void)
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{
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unsigned int cpu = 0;
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int i, num;
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cpus_clear(cpu_possible_map);
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cpu_set(cpu, cpu_possible_map);
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__cpu_number_map[0] = 0;
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__cpu_logical_map[0] = 0;
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/*
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* Do this stupidly for now.. we don't have an easy way to probe
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* for the total number of cores.
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*/
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for (i = 1, num = 0; i < NR_CPUS; i++) {
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cpu_set(i, cpu_possible_map);
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__cpu_number_map[i] = ++num;
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__cpu_logical_map[num] = i;
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}
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printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
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}
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void __init plat_prepare_cpus(unsigned int max_cpus)
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{
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}
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#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
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#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
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#define STBCR_MSTP 0x00000001
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#define STBCR_RESET 0x00000002
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#define STBCR_LTSLP 0x80000000
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#define STBCR_AP_VAL (STBCR_RESET | STBCR_LTSLP)
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void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
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{
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ctrl_outl(entry_point, RESET_REG(cpu));
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if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
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ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
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while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
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;
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/* Start up secondary processor by sending a reset */
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ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
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}
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int plat_smp_processor_id(void)
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{
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return ctrl_inl(0xff000048); /* CPIDR */
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}
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void plat_send_ipi(unsigned int cpu, unsigned int message)
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{
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unsigned long addr = 0xfe410070 + (cpu * 4);
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BUG_ON(cpu >= 4);
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BUG_ON(message >= SMP_MSG_NR);
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ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
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}
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struct ipi_data {
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void (*handler)(void *);
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void *arg;
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unsigned int message;
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};
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static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
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{
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struct ipi_data *id = arg;
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unsigned int cpu = hard_smp_processor_id();
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unsigned int offs = 4 * cpu;
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unsigned int x;
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x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
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x &= (1 << (id->message << 2));
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ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
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id->handler(id->arg);
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return IRQ_HANDLED;
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}
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static struct ipi_data ipi_handlers[SMP_MSG_NR];
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int plat_register_ipi_handler(unsigned int message,
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void (*handler)(void *), void *arg)
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{
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struct ipi_data *id = &ipi_handlers[message];
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BUG_ON(SMP_MSG_NR >= 8);
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BUG_ON(message >= SMP_MSG_NR);
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id->handler = handler;
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id->arg = arg;
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id->message = message;
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return request_irq(104 + message, ipi_interrupt_handler, 0, "IPI", id);
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}
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