875d43e72b
Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
1261 lines
33 KiB
C
1261 lines
33 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/bitops.h>
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/r4kcache.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/war.h>
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static unsigned long icache_size, dcache_size, scache_size;
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/*
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* Dummy cache handling routines for machines without boardcaches
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*/
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static void no_sc_noop(void) {}
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static struct bcache_ops no_sc_ops = {
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.bc_enable = (void *)no_sc_noop,
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.bc_disable = (void *)no_sc_noop,
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.bc_wback_inv = (void *)no_sc_noop,
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.bc_inv = (void *)no_sc_noop
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};
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struct bcache_ops *bcops = &no_sc_ops;
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#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
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#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020)
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#define R4600_HIT_CACHEOP_WAR_IMPL \
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do { \
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
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*(volatile unsigned long *)CKSEG1; \
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if (R4600_V1_HIT_CACHEOP_WAR) \
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__asm__ __volatile__("nop;nop;nop;nop"); \
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} while (0)
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static void (*r4k_blast_dcache_page)(unsigned long addr);
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static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
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{
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R4600_HIT_CACHEOP_WAR_IMPL;
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blast_dcache32_page(addr);
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}
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static inline void r4k_blast_dcache_page_setup(void)
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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if (dc_lsize == 16)
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r4k_blast_dcache_page = blast_dcache16_page;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
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}
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static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
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static inline void r4k_blast_dcache_page_indexed_setup(void)
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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if (dc_lsize == 16)
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r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
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}
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static void (* r4k_blast_dcache)(void);
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static inline void r4k_blast_dcache_setup(void)
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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if (dc_lsize == 16)
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r4k_blast_dcache = blast_dcache16;
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else if (dc_lsize == 32)
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r4k_blast_dcache = blast_dcache32;
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}
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/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
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#define JUMP_TO_ALIGN(order) \
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__asm__ __volatile__( \
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"b\t1f\n\t" \
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".align\t" #order "\n\t" \
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"1:\n\t" \
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)
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#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
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#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
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static inline void blast_r4600_v1_icache32(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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blast_icache32();
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local_irq_restore(flags);
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}
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static inline void tx49_blast_icache32(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.icache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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CACHE32_UNROLL32_ALIGN2;
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/* I'm in even chunk. blast odd chunks */
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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CACHE32_UNROLL32_ALIGN;
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/* I'm in odd chunk. blast even chunks */
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400 * 2)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
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{
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unsigned long flags;
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local_irq_save(flags);
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blast_icache32_page_indexed(page);
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local_irq_restore(flags);
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}
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static inline void tx49_blast_icache32_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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CACHE32_UNROLL32_ALIGN2;
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/* I'm in even chunk. blast odd chunks */
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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CACHE32_UNROLL32_ALIGN;
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/* I'm in odd chunk. blast even chunks */
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400 * 2)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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}
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static void (* r4k_blast_icache_page)(unsigned long addr);
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static inline void r4k_blast_icache_page_setup(void)
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{
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unsigned long ic_lsize = cpu_icache_line_size();
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if (ic_lsize == 16)
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r4k_blast_icache_page = blast_icache16_page;
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else if (ic_lsize == 32)
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r4k_blast_icache_page = blast_icache32_page;
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else if (ic_lsize == 64)
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r4k_blast_icache_page = blast_icache64_page;
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}
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static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
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static inline void r4k_blast_icache_page_indexed_setup(void)
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{
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unsigned long ic_lsize = cpu_icache_line_size();
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if (ic_lsize == 16)
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r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
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else if (ic_lsize == 32) {
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if (TX49XX_ICACHE_INDEX_INV_WAR)
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r4k_blast_icache_page_indexed =
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tx49_blast_icache32_page_indexed;
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else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
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r4k_blast_icache_page_indexed =
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blast_icache32_r4600_v1_page_indexed;
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else
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r4k_blast_icache_page_indexed =
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blast_icache32_page_indexed;
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} else if (ic_lsize == 64)
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r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
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}
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static void (* r4k_blast_icache)(void);
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static inline void r4k_blast_icache_setup(void)
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{
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unsigned long ic_lsize = cpu_icache_line_size();
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if (ic_lsize == 16)
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r4k_blast_icache = blast_icache16;
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else if (ic_lsize == 32) {
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if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
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r4k_blast_icache = blast_r4600_v1_icache32;
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else if (TX49XX_ICACHE_INDEX_INV_WAR)
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r4k_blast_icache = tx49_blast_icache32;
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else
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r4k_blast_icache = blast_icache32;
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} else if (ic_lsize == 64)
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r4k_blast_icache = blast_icache64;
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}
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static void (* r4k_blast_scache_page)(unsigned long addr);
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static inline void r4k_blast_scache_page_setup(void)
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{
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unsigned long sc_lsize = cpu_scache_line_size();
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if (sc_lsize == 16)
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r4k_blast_scache_page = blast_scache16_page;
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else if (sc_lsize == 32)
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r4k_blast_scache_page = blast_scache32_page;
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else if (sc_lsize == 64)
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r4k_blast_scache_page = blast_scache64_page;
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else if (sc_lsize == 128)
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r4k_blast_scache_page = blast_scache128_page;
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}
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static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
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static inline void r4k_blast_scache_page_indexed_setup(void)
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{
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unsigned long sc_lsize = cpu_scache_line_size();
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if (sc_lsize == 16)
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r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
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else if (sc_lsize == 32)
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r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
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else if (sc_lsize == 64)
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r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
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else if (sc_lsize == 128)
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r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
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}
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static void (* r4k_blast_scache)(void);
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static inline void r4k_blast_scache_setup(void)
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{
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unsigned long sc_lsize = cpu_scache_line_size();
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if (sc_lsize == 16)
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r4k_blast_scache = blast_scache16;
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else if (sc_lsize == 32)
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r4k_blast_scache = blast_scache32;
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else if (sc_lsize == 64)
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r4k_blast_scache = blast_scache64;
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else if (sc_lsize == 128)
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r4k_blast_scache = blast_scache128;
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}
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/*
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* This is former mm's flush_cache_all() which really should be
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* flush_cache_vunmap these days ...
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*/
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static inline void local_r4k_flush_cache_all(void * args)
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{
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r4k_blast_dcache();
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r4k_blast_icache();
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}
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static void r4k_flush_cache_all(void)
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{
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if (!cpu_has_dc_aliases)
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return;
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on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
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}
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static inline void local_r4k___flush_cache_all(void * args)
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{
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r4k_blast_dcache();
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r4k_blast_icache();
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switch (current_cpu_data.cputype) {
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case CPU_R4000SC:
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case CPU_R4000MC:
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case CPU_R4400SC:
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case CPU_R4400MC:
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case CPU_R10000:
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case CPU_R12000:
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r4k_blast_scache();
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}
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}
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static void r4k___flush_cache_all(void)
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{
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on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
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}
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static inline void local_r4k_flush_cache_range(void * args)
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{
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struct vm_area_struct *vma = args;
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int exec;
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if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
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return;
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exec = vma->vm_flags & VM_EXEC;
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if (cpu_has_dc_aliases || exec)
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r4k_blast_dcache();
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if (exec)
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r4k_blast_icache();
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}
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static void r4k_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
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}
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static inline void local_r4k_flush_cache_mm(void * args)
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{
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struct mm_struct *mm = args;
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if (!cpu_context(smp_processor_id(), mm))
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return;
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r4k_blast_dcache();
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r4k_blast_icache();
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/*
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* Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
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* only flush the primary caches but R10000 and R12000 behave sane ...
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*/
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if (current_cpu_data.cputype == CPU_R4000SC ||
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current_cpu_data.cputype == CPU_R4000MC ||
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current_cpu_data.cputype == CPU_R4400SC ||
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current_cpu_data.cputype == CPU_R4400MC)
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r4k_blast_scache();
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}
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static void r4k_flush_cache_mm(struct mm_struct *mm)
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{
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if (!cpu_has_dc_aliases)
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return;
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on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
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}
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struct flush_cache_page_args {
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struct vm_area_struct *vma;
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unsigned long page;
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};
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static inline void local_r4k_flush_cache_page(void *args)
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{
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struct flush_cache_page_args *fcp_args = args;
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struct vm_area_struct *vma = fcp_args->vma;
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unsigned long page = fcp_args->page;
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int exec = vma->vm_flags & VM_EXEC;
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struct mm_struct *mm = vma->vm_mm;
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pgd_t *pgdp;
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pmd_t *pmdp;
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pte_t *ptep;
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page &= PAGE_MASK;
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pgdp = pgd_offset(mm, page);
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pmdp = pmd_offset(pgdp, page);
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ptep = pte_offset(pmdp, page);
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/*
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* If the page isn't marked valid, the page cannot possibly be
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* in the cache.
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*/
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if (!(pte_val(*ptep) & _PAGE_PRESENT))
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return;
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/*
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* Doing flushes for another ASID than the current one is
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* too difficult since stupid R4k caches do a TLB translation
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* for every cache flush operation. So we do indexed flushes
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* in that case, which doesn't overly flush the cache too much.
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*/
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if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
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if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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r4k_blast_dcache_page(page);
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if (exec && !cpu_icache_snoops_remote_store)
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r4k_blast_scache_page(page);
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}
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if (exec)
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r4k_blast_icache_page(page);
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return;
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}
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/*
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* Do indexed flush, too much work to get the (possible) TLB refills
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* to work correctly.
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*/
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page = INDEX_BASE + (page & (dcache_size - 1));
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if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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r4k_blast_dcache_page_indexed(page);
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if (exec && !cpu_icache_snoops_remote_store)
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r4k_blast_scache_page_indexed(page);
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}
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if (exec) {
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if (cpu_has_vtag_icache) {
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int cpu = smp_processor_id();
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if (cpu_context(cpu, vma->vm_mm) != 0)
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drop_mmu_context(vma->vm_mm, cpu);
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} else
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r4k_blast_icache_page_indexed(page);
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}
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}
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static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
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{
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struct flush_cache_page_args args;
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/*
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* If ownes no valid ASID yet, cannot possibly have gotten
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* this page into the cache.
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*/
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if (cpu_context(smp_processor_id(), vma->vm_mm) == 0)
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return;
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args.vma = vma;
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args.page = page;
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on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
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}
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static inline void local_r4k_flush_data_cache_page(void * addr)
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{
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r4k_blast_dcache_page((unsigned long) addr);
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}
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static void r4k_flush_data_cache_page(unsigned long addr)
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{
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on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
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}
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struct flush_icache_range_args {
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unsigned long start;
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unsigned long end;
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};
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static inline void local_r4k_flush_icache_range(void *args)
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{
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struct flush_icache_range_args *fir_args = args;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long sc_lsize = current_cpu_data.scache.linesz;
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unsigned long start = fir_args->start;
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|
unsigned long end = fir_args->end;
|
|
unsigned long addr, aend;
|
|
|
|
if (!cpu_has_ic_fills_f_dc) {
|
|
if (end - start > dcache_size) {
|
|
r4k_blast_dcache();
|
|
} else {
|
|
addr = start & ~(dc_lsize - 1);
|
|
aend = (end - 1) & ~(dc_lsize - 1);
|
|
|
|
while (1) {
|
|
/* Hit_Writeback_Inv_D */
|
|
protected_writeback_dcache_line(addr);
|
|
if (addr == aend)
|
|
break;
|
|
addr += dc_lsize;
|
|
}
|
|
}
|
|
|
|
if (!cpu_icache_snoops_remote_store) {
|
|
if (end - start > scache_size) {
|
|
r4k_blast_scache();
|
|
} else {
|
|
addr = start & ~(sc_lsize - 1);
|
|
aend = (end - 1) & ~(sc_lsize - 1);
|
|
|
|
while (1) {
|
|
/* Hit_Writeback_Inv_D */
|
|
protected_writeback_scache_line(addr);
|
|
if (addr == aend)
|
|
break;
|
|
addr += sc_lsize;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (end - start > icache_size)
|
|
r4k_blast_icache();
|
|
else {
|
|
addr = start & ~(ic_lsize - 1);
|
|
aend = (end - 1) & ~(ic_lsize - 1);
|
|
while (1) {
|
|
/* Hit_Invalidate_I */
|
|
protected_flush_icache_line(addr);
|
|
if (addr == aend)
|
|
break;
|
|
addr += ic_lsize;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void r4k_flush_icache_range(unsigned long start, unsigned long end)
|
|
{
|
|
struct flush_icache_range_args args;
|
|
|
|
args.start = start;
|
|
args.end = end;
|
|
|
|
on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
|
|
}
|
|
|
|
/*
|
|
* Ok, this seriously sucks. We use them to flush a user page but don't
|
|
* know the virtual address, so we have to blast away the whole icache
|
|
* which is significantly more expensive than the real thing. Otoh we at
|
|
* least know the kernel address of the page so we can flush it
|
|
* selectivly.
|
|
*/
|
|
|
|
struct flush_icache_page_args {
|
|
struct vm_area_struct *vma;
|
|
struct page *page;
|
|
};
|
|
|
|
static inline void local_r4k_flush_icache_page(void *args)
|
|
{
|
|
struct flush_icache_page_args *fip_args = args;
|
|
struct vm_area_struct *vma = fip_args->vma;
|
|
struct page *page = fip_args->page;
|
|
|
|
/*
|
|
* Tricky ... Because we don't know the virtual address we've got the
|
|
* choice of either invalidating the entire primary and secondary
|
|
* caches or invalidating the secondary caches also. With the subset
|
|
* enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
|
|
* secondary cache will result in any entries in the primary caches
|
|
* also getting invalidated which hopefully is a bit more economical.
|
|
*/
|
|
if (cpu_has_subset_pcaches) {
|
|
unsigned long addr = (unsigned long) page_address(page);
|
|
|
|
r4k_blast_scache_page(addr);
|
|
ClearPageDcacheDirty(page);
|
|
|
|
return;
|
|
}
|
|
|
|
if (!cpu_has_ic_fills_f_dc) {
|
|
unsigned long addr = (unsigned long) page_address(page);
|
|
r4k_blast_dcache_page(addr);
|
|
if (!cpu_icache_snoops_remote_store)
|
|
r4k_blast_scache_page(addr);
|
|
ClearPageDcacheDirty(page);
|
|
}
|
|
|
|
/*
|
|
* We're not sure of the virtual address(es) involved here, so
|
|
* we have to flush the entire I-cache.
|
|
*/
|
|
if (cpu_has_vtag_icache) {
|
|
int cpu = smp_processor_id();
|
|
|
|
if (cpu_context(cpu, vma->vm_mm) != 0)
|
|
drop_mmu_context(vma->vm_mm, cpu);
|
|
} else
|
|
r4k_blast_icache();
|
|
}
|
|
|
|
static void r4k_flush_icache_page(struct vm_area_struct *vma,
|
|
struct page *page)
|
|
{
|
|
struct flush_icache_page_args args;
|
|
|
|
/*
|
|
* If there's no context yet, or the page isn't executable, no I-cache
|
|
* flush is needed.
|
|
*/
|
|
if (!(vma->vm_flags & VM_EXEC))
|
|
return;
|
|
|
|
args.vma = vma;
|
|
args.page = page;
|
|
|
|
on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_DMA_NONCOHERENT
|
|
|
|
static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
|
|
{
|
|
unsigned long end, a;
|
|
|
|
/* Catch bad driver code */
|
|
BUG_ON(size == 0);
|
|
|
|
if (cpu_has_subset_pcaches) {
|
|
unsigned long sc_lsize = current_cpu_data.scache.linesz;
|
|
|
|
if (size >= scache_size) {
|
|
r4k_blast_scache();
|
|
return;
|
|
}
|
|
|
|
a = addr & ~(sc_lsize - 1);
|
|
end = (addr + size - 1) & ~(sc_lsize - 1);
|
|
while (1) {
|
|
flush_scache_line(a); /* Hit_Writeback_Inv_SD */
|
|
if (a == end)
|
|
break;
|
|
a += sc_lsize;
|
|
}
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Either no secondary cache or the available caches don't have the
|
|
* subset property so we have to flush the primary caches
|
|
* explicitly
|
|
*/
|
|
if (size >= dcache_size) {
|
|
r4k_blast_dcache();
|
|
} else {
|
|
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
|
|
|
R4600_HIT_CACHEOP_WAR_IMPL;
|
|
a = addr & ~(dc_lsize - 1);
|
|
end = (addr + size - 1) & ~(dc_lsize - 1);
|
|
while (1) {
|
|
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
|
if (a == end)
|
|
break;
|
|
a += dc_lsize;
|
|
}
|
|
}
|
|
|
|
bc_wback_inv(addr, size);
|
|
}
|
|
|
|
static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
|
|
{
|
|
unsigned long end, a;
|
|
|
|
/* Catch bad driver code */
|
|
BUG_ON(size == 0);
|
|
|
|
if (cpu_has_subset_pcaches) {
|
|
unsigned long sc_lsize = current_cpu_data.scache.linesz;
|
|
|
|
if (size >= scache_size) {
|
|
r4k_blast_scache();
|
|
return;
|
|
}
|
|
|
|
a = addr & ~(sc_lsize - 1);
|
|
end = (addr + size - 1) & ~(sc_lsize - 1);
|
|
while (1) {
|
|
flush_scache_line(a); /* Hit_Writeback_Inv_SD */
|
|
if (a == end)
|
|
break;
|
|
a += sc_lsize;
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (size >= dcache_size) {
|
|
r4k_blast_dcache();
|
|
} else {
|
|
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
|
|
|
R4600_HIT_CACHEOP_WAR_IMPL;
|
|
a = addr & ~(dc_lsize - 1);
|
|
end = (addr + size - 1) & ~(dc_lsize - 1);
|
|
while (1) {
|
|
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
|
if (a == end)
|
|
break;
|
|
a += dc_lsize;
|
|
}
|
|
}
|
|
|
|
bc_inv(addr, size);
|
|
}
|
|
#endif /* CONFIG_DMA_NONCOHERENT */
|
|
|
|
/*
|
|
* While we're protected against bad userland addresses we don't care
|
|
* very much about what happens in that case. Usually a segmentation
|
|
* fault will dump the process later on anyway ...
|
|
*/
|
|
static void local_r4k_flush_cache_sigtramp(void * arg)
|
|
{
|
|
unsigned long ic_lsize = current_cpu_data.icache.linesz;
|
|
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
|
unsigned long sc_lsize = current_cpu_data.scache.linesz;
|
|
unsigned long addr = (unsigned long) arg;
|
|
|
|
R4600_HIT_CACHEOP_WAR_IMPL;
|
|
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
|
if (!cpu_icache_snoops_remote_store)
|
|
protected_writeback_scache_line(addr & ~(sc_lsize - 1));
|
|
protected_flush_icache_line(addr & ~(ic_lsize - 1));
|
|
if (MIPS4K_ICACHE_REFILL_WAR) {
|
|
__asm__ __volatile__ (
|
|
".set push\n\t"
|
|
".set noat\n\t"
|
|
".set mips3\n\t"
|
|
#ifdef CONFIG_32BIT
|
|
"la $at,1f\n\t"
|
|
#endif
|
|
#ifdef CONFIG_64BIT
|
|
"dla $at,1f\n\t"
|
|
#endif
|
|
"cache %0,($at)\n\t"
|
|
"nop; nop; nop\n"
|
|
"1:\n\t"
|
|
".set pop"
|
|
:
|
|
: "i" (Hit_Invalidate_I));
|
|
}
|
|
if (MIPS_CACHE_SYNC_WAR)
|
|
__asm__ __volatile__ ("sync");
|
|
}
|
|
|
|
static void r4k_flush_cache_sigtramp(unsigned long addr)
|
|
{
|
|
on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
|
|
}
|
|
|
|
static void r4k_flush_icache_all(void)
|
|
{
|
|
if (cpu_has_vtag_icache)
|
|
r4k_blast_icache();
|
|
}
|
|
|
|
static inline void rm7k_erratum31(void)
|
|
{
|
|
const unsigned long ic_lsize = 32;
|
|
unsigned long addr;
|
|
|
|
/* RM7000 erratum #31. The icache is screwed at startup. */
|
|
write_c0_taglo(0);
|
|
write_c0_taghi(0);
|
|
|
|
for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
|
|
__asm__ __volatile__ (
|
|
".set noreorder\n\t"
|
|
".set mips3\n\t"
|
|
"cache\t%1, 0(%0)\n\t"
|
|
"cache\t%1, 0x1000(%0)\n\t"
|
|
"cache\t%1, 0x2000(%0)\n\t"
|
|
"cache\t%1, 0x3000(%0)\n\t"
|
|
"cache\t%2, 0(%0)\n\t"
|
|
"cache\t%2, 0x1000(%0)\n\t"
|
|
"cache\t%2, 0x2000(%0)\n\t"
|
|
"cache\t%2, 0x3000(%0)\n\t"
|
|
"cache\t%1, 0(%0)\n\t"
|
|
"cache\t%1, 0x1000(%0)\n\t"
|
|
"cache\t%1, 0x2000(%0)\n\t"
|
|
"cache\t%1, 0x3000(%0)\n\t"
|
|
".set\tmips0\n\t"
|
|
".set\treorder\n\t"
|
|
:
|
|
: "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
|
|
}
|
|
}
|
|
|
|
static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
|
|
"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
|
|
};
|
|
|
|
static void __init probe_pcache(void)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
unsigned int config = read_c0_config();
|
|
unsigned int prid = read_c0_prid();
|
|
unsigned long config1;
|
|
unsigned int lsize;
|
|
|
|
switch (c->cputype) {
|
|
case CPU_R4600: /* QED style two way caches? */
|
|
case CPU_R4700:
|
|
case CPU_R5000:
|
|
case CPU_NEVADA:
|
|
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
|
|
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
|
|
c->icache.ways = 2;
|
|
c->icache.waybit = ffs(icache_size/2) - 1;
|
|
|
|
dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
|
|
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
|
|
c->dcache.ways = 2;
|
|
c->dcache.waybit= ffs(dcache_size/2) - 1;
|
|
|
|
c->options |= MIPS_CPU_CACHE_CDEX_P;
|
|
break;
|
|
|
|
case CPU_R5432:
|
|
case CPU_R5500:
|
|
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
|
|
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
|
|
c->icache.ways = 2;
|
|
c->icache.waybit= 0;
|
|
|
|
dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
|
|
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
|
|
c->dcache.ways = 2;
|
|
c->dcache.waybit = 0;
|
|
|
|
c->options |= MIPS_CPU_CACHE_CDEX_P;
|
|
break;
|
|
|
|
case CPU_TX49XX:
|
|
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
|
|
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
|
|
c->icache.ways = 4;
|
|
c->icache.waybit= 0;
|
|
|
|
dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
|
|
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
|
|
c->dcache.ways = 4;
|
|
c->dcache.waybit = 0;
|
|
|
|
c->options |= MIPS_CPU_CACHE_CDEX_P;
|
|
break;
|
|
|
|
case CPU_R4000PC:
|
|
case CPU_R4000SC:
|
|
case CPU_R4000MC:
|
|
case CPU_R4400PC:
|
|
case CPU_R4400SC:
|
|
case CPU_R4400MC:
|
|
case CPU_R4300:
|
|
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
|
|
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
|
|
c->icache.ways = 1;
|
|
c->icache.waybit = 0; /* doesn't matter */
|
|
|
|
dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
|
|
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
|
|
c->dcache.ways = 1;
|
|
c->dcache.waybit = 0; /* does not matter */
|
|
|
|
c->options |= MIPS_CPU_CACHE_CDEX_P;
|
|
break;
|
|
|
|
case CPU_R10000:
|
|
case CPU_R12000:
|
|
icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
|
|
c->icache.linesz = 64;
|
|
c->icache.ways = 2;
|
|
c->icache.waybit = 0;
|
|
|
|
dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
|
|
c->dcache.linesz = 32;
|
|
c->dcache.ways = 2;
|
|
c->dcache.waybit = 0;
|
|
|
|
c->options |= MIPS_CPU_PREFETCH;
|
|
break;
|
|
|
|
case CPU_VR4133:
|
|
write_c0_config(config & ~CONF_EB);
|
|
case CPU_VR4131:
|
|
/* Workaround for cache instruction bug of VR4131 */
|
|
if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
|
|
c->processor_id == 0x0c82U) {
|
|
config &= ~0x00000030U;
|
|
config |= 0x00410000U;
|
|
write_c0_config(config);
|
|
}
|
|
icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
|
|
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
|
|
c->icache.ways = 2;
|
|
c->icache.waybit = ffs(icache_size/2) - 1;
|
|
|
|
dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
|
|
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
|
|
c->dcache.ways = 2;
|
|
c->dcache.waybit = ffs(dcache_size/2) - 1;
|
|
|
|
c->options |= MIPS_CPU_CACHE_CDEX_P;
|
|
break;
|
|
|
|
case CPU_VR41XX:
|
|
case CPU_VR4111:
|
|
case CPU_VR4121:
|
|
case CPU_VR4122:
|
|
case CPU_VR4181:
|
|
case CPU_VR4181A:
|
|
icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
|
|
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
|
|
c->icache.ways = 1;
|
|
c->icache.waybit = 0; /* doesn't matter */
|
|
|
|
dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
|
|
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
|
|
c->dcache.ways = 1;
|
|
c->dcache.waybit = 0; /* does not matter */
|
|
|
|
c->options |= MIPS_CPU_CACHE_CDEX_P;
|
|
break;
|
|
|
|
case CPU_RM7000:
|
|
rm7k_erratum31();
|
|
|
|
case CPU_RM9000:
|
|
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
|
|
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
|
|
c->icache.ways = 4;
|
|
c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
|
|
|
|
dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
|
|
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
|
|
c->dcache.ways = 4;
|
|
c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
|
|
|
|
#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
|
|
c->options |= MIPS_CPU_CACHE_CDEX_P;
|
|
#endif
|
|
c->options |= MIPS_CPU_PREFETCH;
|
|
break;
|
|
|
|
default:
|
|
if (!(config & MIPS_CONF_M))
|
|
panic("Don't know how to probe P-caches on this cpu.");
|
|
|
|
/*
|
|
* So we seem to be a MIPS32 or MIPS64 CPU
|
|
* So let's probe the I-cache ...
|
|
*/
|
|
config1 = read_c0_config1();
|
|
|
|
if ((lsize = ((config1 >> 19) & 7)))
|
|
c->icache.linesz = 2 << lsize;
|
|
else
|
|
c->icache.linesz = lsize;
|
|
c->icache.sets = 64 << ((config1 >> 22) & 7);
|
|
c->icache.ways = 1 + ((config1 >> 16) & 7);
|
|
|
|
icache_size = c->icache.sets *
|
|
c->icache.ways *
|
|
c->icache.linesz;
|
|
c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
|
|
|
|
if (config & 0x8) /* VI bit */
|
|
c->icache.flags |= MIPS_CACHE_VTAG;
|
|
|
|
/*
|
|
* Now probe the MIPS32 / MIPS64 data cache.
|
|
*/
|
|
c->dcache.flags = 0;
|
|
|
|
if ((lsize = ((config1 >> 10) & 7)))
|
|
c->dcache.linesz = 2 << lsize;
|
|
else
|
|
c->dcache.linesz= lsize;
|
|
c->dcache.sets = 64 << ((config1 >> 13) & 7);
|
|
c->dcache.ways = 1 + ((config1 >> 7) & 7);
|
|
|
|
dcache_size = c->dcache.sets *
|
|
c->dcache.ways *
|
|
c->dcache.linesz;
|
|
c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
|
|
|
|
c->options |= MIPS_CPU_PREFETCH;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Processor configuration sanity check for the R4000SC erratum
|
|
* #5. With page sizes larger than 32kB there is no possibility
|
|
* to get a VCE exception anymore so we don't care about this
|
|
* misconfiguration. The case is rather theoretical anyway;
|
|
* presumably no vendor is shipping his hardware in the "bad"
|
|
* configuration.
|
|
*/
|
|
if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
|
|
!(config & CONF_SC) && c->icache.linesz != 16 &&
|
|
PAGE_SIZE <= 0x8000)
|
|
panic("Improper R4000SC processor configuration detected");
|
|
|
|
/* compute a couple of other cache variables */
|
|
c->icache.waysize = icache_size / c->icache.ways;
|
|
c->dcache.waysize = dcache_size / c->dcache.ways;
|
|
|
|
c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
|
|
c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
|
|
|
|
/*
|
|
* R10000 and R12000 P-caches are odd in a positive way. They're 32kB
|
|
* 2-way virtually indexed so normally would suffer from aliases. So
|
|
* normally they'd suffer from aliases but magic in the hardware deals
|
|
* with that for us so we don't need to take care ourselves.
|
|
*/
|
|
if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000)
|
|
if (c->dcache.waysize > PAGE_SIZE)
|
|
c->dcache.flags |= MIPS_CACHE_ALIASES;
|
|
|
|
switch (c->cputype) {
|
|
case CPU_20KC:
|
|
/*
|
|
* Some older 20Kc chips doesn't have the 'VI' bit in
|
|
* the config register.
|
|
*/
|
|
c->icache.flags |= MIPS_CACHE_VTAG;
|
|
break;
|
|
|
|
case CPU_AU1500:
|
|
c->icache.flags |= MIPS_CACHE_IC_F_DC;
|
|
break;
|
|
}
|
|
|
|
printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
|
|
icache_size >> 10,
|
|
cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
|
|
way_string[c->icache.ways], c->icache.linesz);
|
|
|
|
printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
|
|
dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
|
|
}
|
|
|
|
/*
|
|
* If you even _breathe_ on this function, look at the gcc output and make sure
|
|
* it does not pop things on and off the stack for the cache sizing loop that
|
|
* executes in KSEG1 space or else you will crash and burn badly. You have
|
|
* been warned.
|
|
*/
|
|
static int __init probe_scache(void)
|
|
{
|
|
extern unsigned long stext;
|
|
unsigned long flags, addr, begin, end, pow2;
|
|
unsigned int config = read_c0_config();
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
int tmp;
|
|
|
|
if (config & CONF_SC)
|
|
return 0;
|
|
|
|
begin = (unsigned long) &stext;
|
|
begin &= ~((4 * 1024 * 1024) - 1);
|
|
end = begin + (4 * 1024 * 1024);
|
|
|
|
/*
|
|
* This is such a bitch, you'd think they would make it easy to do
|
|
* this. Away you daemons of stupidity!
|
|
*/
|
|
local_irq_save(flags);
|
|
|
|
/* Fill each size-multiple cache line with a valid tag. */
|
|
pow2 = (64 * 1024);
|
|
for (addr = begin; addr < end; addr = (begin + pow2)) {
|
|
unsigned long *p = (unsigned long *) addr;
|
|
__asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
|
|
pow2 <<= 1;
|
|
}
|
|
|
|
/* Load first line with zero (therefore invalid) tag. */
|
|
write_c0_taglo(0);
|
|
write_c0_taghi(0);
|
|
__asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
|
|
cache_op(Index_Store_Tag_I, begin);
|
|
cache_op(Index_Store_Tag_D, begin);
|
|
cache_op(Index_Store_Tag_SD, begin);
|
|
|
|
/* Now search for the wrap around point. */
|
|
pow2 = (128 * 1024);
|
|
tmp = 0;
|
|
for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
|
|
cache_op(Index_Load_Tag_SD, addr);
|
|
__asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
|
|
if (!read_c0_taglo())
|
|
break;
|
|
pow2 <<= 1;
|
|
}
|
|
local_irq_restore(flags);
|
|
addr -= begin;
|
|
|
|
scache_size = addr;
|
|
c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
|
|
c->scache.ways = 1;
|
|
c->dcache.waybit = 0; /* does not matter */
|
|
|
|
return 1;
|
|
}
|
|
|
|
typedef int (*probe_func_t)(unsigned long);
|
|
extern int r5k_sc_init(void);
|
|
extern int rm7k_sc_init(void);
|
|
|
|
static void __init setup_scache(void)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
unsigned int config = read_c0_config();
|
|
probe_func_t probe_scache_kseg1;
|
|
int sc_present = 0;
|
|
|
|
/*
|
|
* Do the probing thing on R4000SC and R4400SC processors. Other
|
|
* processors don't have a S-cache that would be relevant to the
|
|
* Linux memory managment.
|
|
*/
|
|
switch (c->cputype) {
|
|
case CPU_R4000SC:
|
|
case CPU_R4000MC:
|
|
case CPU_R4400SC:
|
|
case CPU_R4400MC:
|
|
probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache));
|
|
sc_present = probe_scache_kseg1(config);
|
|
if (sc_present)
|
|
c->options |= MIPS_CPU_CACHE_CDEX_S;
|
|
break;
|
|
|
|
case CPU_R10000:
|
|
case CPU_R12000:
|
|
scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
|
|
c->scache.linesz = 64 << ((config >> 13) & 1);
|
|
c->scache.ways = 2;
|
|
c->scache.waybit= 0;
|
|
sc_present = 1;
|
|
break;
|
|
|
|
case CPU_R5000:
|
|
case CPU_NEVADA:
|
|
#ifdef CONFIG_R5000_CPU_SCACHE
|
|
r5k_sc_init();
|
|
#endif
|
|
return;
|
|
|
|
case CPU_RM7000:
|
|
case CPU_RM9000:
|
|
#ifdef CONFIG_RM7000_CPU_SCACHE
|
|
rm7k_sc_init();
|
|
#endif
|
|
return;
|
|
|
|
default:
|
|
sc_present = 0;
|
|
}
|
|
|
|
if (!sc_present)
|
|
return;
|
|
|
|
if ((c->isa_level == MIPS_CPU_ISA_M32 ||
|
|
c->isa_level == MIPS_CPU_ISA_M64) &&
|
|
!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
|
|
panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
|
|
|
|
/* compute a couple of other cache variables */
|
|
c->scache.waysize = scache_size / c->scache.ways;
|
|
|
|
c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
|
|
|
|
printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
|
|
scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
|
|
|
|
c->options |= MIPS_CPU_SUBSET_CACHES;
|
|
}
|
|
|
|
static inline void coherency_setup(void)
|
|
{
|
|
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
|
|
|
/*
|
|
* c0_status.cu=0 specifies that updates by the sc instruction use
|
|
* the coherency mode specified by the TLB; 1 means cachable
|
|
* coherent update on write will be used. Not all processors have
|
|
* this bit and; some wire it to zero, others like Toshiba had the
|
|
* silly idea of putting something else there ...
|
|
*/
|
|
switch (current_cpu_data.cputype) {
|
|
case CPU_R4000PC:
|
|
case CPU_R4000SC:
|
|
case CPU_R4000MC:
|
|
case CPU_R4400PC:
|
|
case CPU_R4400SC:
|
|
case CPU_R4400MC:
|
|
clear_c0_config(CONF_CU);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void __init ld_mmu_r4xx0(void)
|
|
{
|
|
extern void build_clear_page(void);
|
|
extern void build_copy_page(void);
|
|
extern char except_vec2_generic;
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
|
|
/* Default cache error handler for R4000 and R5000 family */
|
|
memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80);
|
|
memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
|
|
|
|
probe_pcache();
|
|
setup_scache();
|
|
|
|
if (c->dcache.sets * c->dcache.ways > PAGE_SIZE)
|
|
c->dcache.flags |= MIPS_CACHE_ALIASES;
|
|
|
|
r4k_blast_dcache_page_setup();
|
|
r4k_blast_dcache_page_indexed_setup();
|
|
r4k_blast_dcache_setup();
|
|
r4k_blast_icache_page_setup();
|
|
r4k_blast_icache_page_indexed_setup();
|
|
r4k_blast_icache_setup();
|
|
r4k_blast_scache_page_setup();
|
|
r4k_blast_scache_page_indexed_setup();
|
|
r4k_blast_scache_setup();
|
|
|
|
/*
|
|
* Some MIPS32 and MIPS64 processors have physically indexed caches.
|
|
* This code supports virtually indexed processors and will be
|
|
* unnecessarily inefficient on physically indexed processors.
|
|
*/
|
|
shm_align_mask = max_t( unsigned long,
|
|
c->dcache.sets * c->dcache.linesz - 1,
|
|
PAGE_SIZE - 1);
|
|
|
|
flush_cache_all = r4k_flush_cache_all;
|
|
__flush_cache_all = r4k___flush_cache_all;
|
|
flush_cache_mm = r4k_flush_cache_mm;
|
|
flush_cache_page = r4k_flush_cache_page;
|
|
flush_icache_page = r4k_flush_icache_page;
|
|
flush_cache_range = r4k_flush_cache_range;
|
|
|
|
flush_cache_sigtramp = r4k_flush_cache_sigtramp;
|
|
flush_icache_all = r4k_flush_icache_all;
|
|
flush_data_cache_page = r4k_flush_data_cache_page;
|
|
flush_icache_range = r4k_flush_icache_range;
|
|
|
|
#ifdef CONFIG_DMA_NONCOHERENT
|
|
_dma_cache_wback_inv = r4k_dma_cache_wback_inv;
|
|
_dma_cache_wback = r4k_dma_cache_wback_inv;
|
|
_dma_cache_inv = r4k_dma_cache_inv;
|
|
#endif
|
|
|
|
__flush_cache_all();
|
|
coherency_setup();
|
|
|
|
build_clear_page();
|
|
build_copy_page();
|
|
}
|