19ca5d27e1
The SA1100 RTC alarm can be configured to wake up the CPU from sleep mode, and the RTC driver has been using the API to configure this mode. Unfortunately, the code was which sets the required bit in the hardware was missing. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
349 lines
7.1 KiB
C
349 lines
7.1 KiB
C
/*
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* linux/arch/arm/mach-sa1100/irq.c
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*
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* Copyright (C) 1999-2001 Nicolas Pitre
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*
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* Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/ptrace.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include "generic.h"
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/*
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* SA1100 GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* Use this instead of directly setting GRER/GFER.
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*/
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static int GPIO_IRQ_rising_edge;
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static int GPIO_IRQ_falling_edge;
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static int GPIO_IRQ_mask = (1 << 11) - 1;
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/*
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* To get the GPIO number from an IRQ number
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*/
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#define GPIO_11_27_IRQ(i) ((i) - 21)
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#define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
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static int sa1100_gpio_type(unsigned int irq, unsigned int type)
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{
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unsigned int mask;
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if (irq <= 10)
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mask = 1 << irq;
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else
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mask = GPIO11_27_MASK(irq);
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if (type == IRQT_PROBE) {
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if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
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return 0;
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type = __IRQT_RISEDGE | __IRQT_FALEDGE;
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}
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if (type & __IRQT_RISEDGE) {
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GPIO_IRQ_rising_edge |= mask;
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} else
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GPIO_IRQ_rising_edge &= ~mask;
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if (type & __IRQT_FALEDGE) {
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GPIO_IRQ_falling_edge |= mask;
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} else
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GPIO_IRQ_falling_edge &= ~mask;
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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return 0;
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}
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/*
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* GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
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*/
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static void sa1100_low_gpio_ack(unsigned int irq)
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{
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GEDR = (1 << irq);
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}
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static void sa1100_low_gpio_mask(unsigned int irq)
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{
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ICMR &= ~(1 << irq);
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}
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static void sa1100_low_gpio_unmask(unsigned int irq)
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{
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ICMR |= 1 << irq;
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}
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static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
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{
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if (on)
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PWER |= 1 << irq;
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else
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PWER &= ~(1 << irq);
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return 0;
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}
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static struct irqchip sa1100_low_gpio_chip = {
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.ack = sa1100_low_gpio_ack,
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.mask = sa1100_low_gpio_mask,
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.unmask = sa1100_low_gpio_unmask,
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.set_type = sa1100_gpio_type,
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.set_wake = sa1100_low_gpio_wake,
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};
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/*
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* IRQ11 (GPIO11 through 27) handler. We enter here with the
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* irq_controller_lock held, and IRQs disabled. Decode the IRQ
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* and call the handler.
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*/
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static void
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sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int mask;
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mask = GEDR & 0xfffff800;
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do {
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/*
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* clear down all currently active IRQ sources.
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* We will be processing them all.
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*/
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GEDR = mask;
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irq = IRQ_GPIO11;
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desc = irq_desc + irq;
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mask >>= 11;
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do {
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if (mask & 1)
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desc_handle_irq(irq, desc, regs);
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mask >>= 1;
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irq++;
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desc++;
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} while (mask);
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mask = GEDR & 0xfffff800;
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} while (mask);
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}
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/*
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* Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
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* In addition, the IRQs are all collected up into one bit in the
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* interrupt controller registers.
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*/
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static void sa1100_high_gpio_ack(unsigned int irq)
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{
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unsigned int mask = GPIO11_27_MASK(irq);
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GEDR = mask;
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}
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static void sa1100_high_gpio_mask(unsigned int irq)
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{
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unsigned int mask = GPIO11_27_MASK(irq);
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GPIO_IRQ_mask &= ~mask;
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GRER &= ~mask;
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GFER &= ~mask;
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}
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static void sa1100_high_gpio_unmask(unsigned int irq)
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{
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unsigned int mask = GPIO11_27_MASK(irq);
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GPIO_IRQ_mask |= mask;
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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}
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static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
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{
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if (on)
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PWER |= GPIO11_27_MASK(irq);
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else
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PWER &= ~GPIO11_27_MASK(irq);
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return 0;
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}
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static struct irqchip sa1100_high_gpio_chip = {
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.ack = sa1100_high_gpio_ack,
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.mask = sa1100_high_gpio_mask,
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.unmask = sa1100_high_gpio_unmask,
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.set_type = sa1100_gpio_type,
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.set_wake = sa1100_high_gpio_wake,
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};
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/*
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* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
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* this is for internal IRQs i.e. from 11 to 31.
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*/
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static void sa1100_mask_irq(unsigned int irq)
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{
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ICMR &= ~(1 << irq);
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}
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static void sa1100_unmask_irq(unsigned int irq)
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{
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ICMR |= (1 << irq);
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}
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/*
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* Apart form GPIOs, only the RTC alarm can be a wakeup event.
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*/
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static int sa1100_set_wake(unsigned int irq, unsigned int on)
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{
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if (irq == IRQ_RTCAlrm) {
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if (on)
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PWER |= PWER_RTC;
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else
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PWER &= ~PWER_RTC;
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return 0;
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}
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return -EINVAL;
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}
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static struct irqchip sa1100_normal_chip = {
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.ack = sa1100_mask_irq,
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.mask = sa1100_mask_irq,
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.unmask = sa1100_unmask_irq,
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.set_wake = sa1100_set_wake,
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};
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static struct resource irq_resource = {
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.name = "irqs",
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.start = 0x90050000,
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.end = 0x9005ffff,
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};
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static struct sa1100irq_state {
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unsigned int saved;
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unsigned int icmr;
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unsigned int iclr;
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unsigned int iccr;
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} sa1100irq_state;
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static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct sa1100irq_state *st = &sa1100irq_state;
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st->saved = 1;
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st->icmr = ICMR;
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st->iclr = ICLR;
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st->iccr = ICCR;
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/*
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* Disable all GPIO-based interrupts.
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*/
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ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
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IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
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IC_GPIO1|IC_GPIO0);
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/*
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* Set the appropriate edges for wakeup.
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*/
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GRER = PWER & GPIO_IRQ_rising_edge;
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GFER = PWER & GPIO_IRQ_falling_edge;
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/*
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* Clear any pending GPIO interrupts.
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*/
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GEDR = GEDR;
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return 0;
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}
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static int sa1100irq_resume(struct sys_device *dev)
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{
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struct sa1100irq_state *st = &sa1100irq_state;
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if (st->saved) {
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ICCR = st->iccr;
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ICLR = st->iclr;
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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ICMR = st->icmr;
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}
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return 0;
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}
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static struct sysdev_class sa1100irq_sysclass = {
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set_kset_name("sa11x0-irq"),
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.suspend = sa1100irq_suspend,
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.resume = sa1100irq_resume,
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};
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static struct sys_device sa1100irq_device = {
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.id = 0,
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.cls = &sa1100irq_sysclass,
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};
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static int __init sa1100irq_init_devicefs(void)
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{
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sysdev_class_register(&sa1100irq_sysclass);
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return sysdev_register(&sa1100irq_device);
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}
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device_initcall(sa1100irq_init_devicefs);
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void __init sa1100_init_irq(void)
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{
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unsigned int irq;
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request_resource(&iomem_resource, &irq_resource);
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/* disable all IRQs */
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ICMR = 0;
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/* all IRQs are IRQ, not FIQ */
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ICLR = 0;
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/* clear all GPIO edge detects */
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GFER = 0;
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GRER = 0;
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GEDR = -1;
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/*
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* Whatever the doc says, this has to be set for the wait-on-irq
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* instruction to work... on a SA1100 rev 9 at least.
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*/
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ICCR = 1;
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for (irq = 0; irq <= 10; irq++) {
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set_irq_chip(irq, &sa1100_low_gpio_chip);
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set_irq_handler(irq, do_edge_IRQ);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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for (irq = 12; irq <= 31; irq++) {
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set_irq_chip(irq, &sa1100_normal_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, IRQF_VALID);
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}
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for (irq = 32; irq <= 48; irq++) {
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set_irq_chip(irq, &sa1100_high_gpio_chip);
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set_irq_handler(irq, do_edge_IRQ);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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/*
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* Install handler for GPIO 11-27 edge detect interrupts
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*/
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set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
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set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
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}
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