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android_kernel_xiaomi_sm8350/arch/powerpc/boot/dts/mpc8610_hpcd.dts
Anton Vorontsov d2998c2c36 powerpc/86xx: add MMC SPI support for MPC8610HPCD boards 
This patch adds spi and mmc-spi-slot nodes, plus a gpio-controller for
PIXIS' sdcsr bank that is used for managing SPI chip-select and for
reading card's states.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Cc: Kumar Gala <galak@gate.crashing.org>
Cc: David Brownell <david-b@pacbell.net>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-19 16:46:04 -07:00

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/*
* MPC8610 HPCD Device Tree Source
*
* Copyright 2007-2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License Version 2 as published
* by the Free Software Foundation.
*/
/dts-v1/;
/ {
model = "MPC8610HPCD";
compatible = "fsl,MPC8610HPCD";
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8610@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>; // L1
i-cache-size = <32768>; // L1
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512M at 0x0
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xf8000000 0x08000000
1 0 0xf0000000 0x08000000
2 0 0xe8400000 0x00008000
4 0 0xe8440000 0x00008000
5 0 0xe8480000 0x00008000
6 0 0xe84c0000 0x00008000
3 0 0xe8000000 0x00000020>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
flash@1,0 {
compatible = "cfi-flash";
reg = <1 0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
flash@2,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <2 0 0x8000>;
};
flash@4,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <4 0 0x8000>;
};
flash@5,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <5 0 0x8000>;
};
flash@6,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <6 0 0x8000>;
};
board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,fpga-pixis";
reg = <3 0 0x20>;
ranges = <0 3 0 0x20>;
sdcsr_pio: gpio-controller@a {
#gpio-cells = <2>;
compatible = "fsl,fpga-pixis-gpio-bank";
reg = <0xa 1>;
gpio-controller;
};
};
};
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8610-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
bus-frequency = <0>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8610-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
cs4270:codec@4f {
compatible = "cirrus,cs4270";
reg = <0x4f>;
/* MCLK source is a stand-alone oscillator */
clock-frequency = <12288000>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
spi@7000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8610-spi", "fsl,spi";
reg = <0x7000 0x40>;
cell-index = <0>;
interrupts = <59 2>;
interrupt-parent = <&mpic>;
mode = "cpu";
gpios = <&sdcsr_pio 7 0>;
mmc-slot@0 {
compatible = "fsl,mpc8610hpcd-mmc-slot",
"mmc-spi-slot";
reg = <0>;
gpios = <&sdcsr_pio 0 1 /* nCD */
&sdcsr_pio 1 0>; /* WP */
voltage-ranges = <3300 3300>;
spi-max-frequency = <50000000>;
};
};
display@2c000 {
compatible = "fsl,diu";
reg = <0x2c000 100>;
interrupts = <72 2>;
interrupt-parent = <&mpic>;
};
mpic: interrupt-controller@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
msi@41600 {
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 {
compatible = "fsl,mpc8610-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
wdt@e4000 {
compatible = "fsl,mpc8610-wdt";
reg = <0xe4000 0x100>;
};
ssi@16000 {
compatible = "fsl,mpc8610-ssi";
cell-index = <0>;
reg = <0x16000 0x100>;
interrupt-parent = <&mpic>;
interrupts = <62 2>;
fsl,mode = "i2s-slave";
codec-handle = <&cs4270>;
fsl,playback-dma = <&dma00>;
fsl,capture-dma = <&dma01>;
fsl,fifo-depth = <8>;
};
ssi@16100 {
compatible = "fsl,mpc8610-ssi";
cell-index = <1>;
reg = <0x16100 0x100>;
interrupt-parent = <&mpic>;
interrupts = <63 2>;
fsl,fifo-depth = <8>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
cell-index = <0>;
reg = <0x21300 0x4>; /* DMA general status register */
ranges = <0x0 0x21100 0x200>;
dma00: dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,ssi-dma-channel";
cell-index = <0>;
reg = <0x0 0x80>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma01: dma-channel@1 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,ssi-dma-channel";
cell-index = <1>;
reg = <0x80 0x80>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@2 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <2>;
reg = <0x100 0x80>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@3 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <3>;
reg = <0x180 0x80>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
cell-index = <1>;
reg = <0xc300 0x4>; /* DMA general status register */
ranges = <0x0 0xc100 0x200>;
dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <0>;
reg = <0x0 0x80>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@1 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <1>;
reg = <0x80 0x80>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@2 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <2>;
reg = <0x100 0x80>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@3 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <3>;
reg = <0x180 0x80>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
};
pci0: pci@e0008000 {
compatible = "fsl,mpc8610-pci";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008000 0x1000>;
bus-range = <0 0>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0 0 1 &mpic 4 1
0x8800 0 0 2 &mpic 5 1
0x8800 0 0 3 &mpic 6 1
0x8800 0 0 4 &mpic 7 1
/* IDSEL 0x12 */
0x9000 0 0 1 &mpic 5 1
0x9000 0 0 2 &mpic 6 1
0x9000 0 0 3 &mpic 7 1
0x9000 0 0 4 &mpic 4 1
>;
};
pci1: pcie@e000a000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe000a000 0x1000>;
bus-range = <1 3>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x1b */
0xd800 0 0 1 &mpic 2 1
/* IDSEL 0x1c*/
0xe000 0 0 1 &mpic 1 1
0xe000 0 0 2 &mpic 1 1
0xe000 0 0 3 &mpic 1 1
0xe000 0 0 4 &mpic 1 1
/* IDSEL 0x1f */
0xf800 0 0 1 &mpic 3 2
0xf800 0 0 2 &mpic 0 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000
0x0 0x10000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000
0x0 0x10000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00100000>;
isa@1e {
device_type = "isa";
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0 0 0 0>;
ranges = <1 0 0x01000000 0 0
0x00001000>;
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 0x70 2>;
};
};
};
};
};
pci2: pcie@e0009000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8641-pcie";
reg = <0xe0009000 0x00001000>;
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0000 0 0 1 &mpic 4 1
0x0000 0 0 2 &mpic 5 1
0x0000 0 0 3 &mpic 6 1
0x0000 0 0 4 &mpic 7 1>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
clock-frequency = <33333333>;
};
};
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