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android_kernel_xiaomi_sm8350/arch/powerpc/boot/dts/socrates.dts
Kumar Gala b1b6802586 powerpc/fsl: Removed reg property from 85xx/86xx soc node 
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level.  It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-19 00:50:29 -05:00

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/*
* Device Tree Source for the Socrates board (MPC8544).
*
* Copyright (c) 2008 Emcraft Systems.
* Sergei Poselenov, <sposelenov@emcraft.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "abb,socrates";
compatible = "abb,socrates";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8544@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000>; // Filled in by U-Boot
};
soc8544@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x00000000 0xe0000000 0x00100000>;
bus-frequency = <0>; // Filled in by U-Boot
compatible = "fsl,mpc8544-immr", "simple-bus";
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
ecm@1000 {
compatible = "fsl,mpc8544-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8544-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8544-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8544-i2c", "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
fsl,preserve-clocking;
dtt@28 {
compatible = "winbond,w83782d";
reg = <0x28>;
};
rtc@32 {
compatible = "epson,rx8025";
reg = <0x32>;
interrupts = <7 1>;
interrupt-parent = <&mpic>;
};
dtt@4c {
compatible = "dallas,ds75";
reg = <0x4c>;
};
ts@4a {
compatible = "ti,tsc2003";
reg = <0x4a>;
interrupt-parent = <&mpic>;
interrupts = <8 1>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl,mpc8544-i2c", "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
fsl,preserve-clocking;
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <0 1>;
reg = <0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <0 1>;
reg = <1>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
};
};
};
enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
tbi-handle = <&tbi1>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
};
localbus {
compatible = "fsl,mpc8544-localbus",
"fsl,pq3-localbus",
"simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xe0005000 0x40>;
ranges = <0 0 0xfc000000 0x04000000
2 0 0xc8000000 0x04000000
3 0 0xc0000000 0x00100000
>; /* Overwritten by U-Boot */
nor_flash@0,0 {
compatible = "amd,s29gl256n", "cfi-flash";
bank-width = <2>;
reg = <0x0 0x000000 0x4000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x1e0000>;
read-only;
};
partition@1e0000 {
label = "dtb";
reg = <0x1e0000 0x20000>;
};
partition@200000 {
label = "root";
reg = <0x200000 0x200000>;
};
partition@400000 {
label = "user";
reg = <0x400000 0x3b80000>;
};
partition@3f80000 {
label = "env";
reg = <0x3f80000 0x40000>;
read-only;
};
partition@3fc0000 {
label = "u-boot";
reg = <0x3fc0000 0x40000>;
read-only;
};
};
display@2,0 {
compatible = "fujitsu,lime";
reg = <2 0x0 0x4000000>;
interrupt-parent = <&mpic>;
interrupts = <6 1>;
};
fpga_pic: fpga-pic@3,10 {
compatible = "abb,socrates-fpga-pic";
reg = <3 0x10 0x10>;
interrupt-controller;
/* IRQs 2, 10, 11, active low, level-sensitive */
interrupts = <2 1 10 1 11 1>;
interrupt-parent = <&mpic>;
#interrupt-cells = <3>;
};
spi@3,60 {
compatible = "abb,socrates-spi";
reg = <3 0x60 0x10>;
interrupts = <8 4 0>; // number, type, routing
interrupt-parent = <&fpga_pic>;
};
nand@3,70 {
compatible = "abb,socrates-nand";
reg = <3 0x70 0x04>;
bank-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
data@0 {
label = "data";
reg = <0x0 0x40000000>;
};
};
can@3,100 {
compatible = "philips,sja1000";
reg = <3 0x100 0x80>;
interrupts = <2 8 1>; // number, type, routing
interrupt-parent = <&fpga_pic>;
};
};
pci0: pci@e0008000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
reg = <0xe0008000 0x1000>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0x0 0x0 1 &mpic 5 1
/* IDSEL 0x12 */
0x9000 0x0 0x0 1 &mpic 4 1>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
};
};
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