474dad54ba
Update the DaVinci GPIO code to work better on non-dm6446 parts, notably the dm355: - Only handle the number of GPIOs the chip actually has. So for example on dm6467, GPIO-42 is the last GPIO, and trying to use GPIO-43 now fails cleanly; or GPIO-72 on dm6446. - Enable GPIO interrupts on each 16-bit GPIO-irq bank ... previously, only the first five were enabled, so GPIO-80 and above (on dm355) wouldn't trigger IRQs. - Use the right IRQ for each GPIO bank. The wrong values were used for dm355 chips, so GPIO IRQs got routed incorrectly. - Handle up to four pairs of 16-bit GPIO banks ... previously only three were handled, so accessing GPIO-96 and up (e.g. on dm355) would oops. - Update several comments that were dm6446-specific. Verified by receiving GPIO-1 (dm9000) and GPIO-5 (msp430) IRQs on the DM355 EVM. One thing this doesn't do is handle the way some of the GPIO numbers on dm6467 are reserved but aren't valid as GPIOs. Some bitmap logic could fix that if needed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
155 lines
4.3 KiB
C
155 lines
4.3 KiB
C
/*
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* TI DaVinci GPIO Support
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*
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* Copyright (c) 2006 David Brownell
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DAVINCI_GPIO_H
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#define __DAVINCI_GPIO_H
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#include <linux/io.h>
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#include <asm-generic/gpio.h>
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#include <mach/irqs.h>
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#define DAVINCI_GPIO_BASE 0x01C67000
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/*
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* basic gpio routines
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*
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* board-specific init should be done by arch/.../.../board-XXX.c (maybe
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* initializing banks together) rather than boot loaders; kexec() won't
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* go through boot loaders.
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*
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* the gpio clock will be turned on when gpios are used, and you may also
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* need to pay attention to PINMUX registers to be sure those pins are
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* used as gpios, not with other peripherals.
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*
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* On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
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* and maybe for later updates, code may write GPIO(N). These may be
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* all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip
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* may not support all the GPIOs in that range.
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*
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* GPIOs can also be on external chips, numbered after the ones built-in
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* to the DaVinci chip. For now, they won't be usable as IRQ sources.
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*/
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#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
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struct gpio_controller {
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u32 dir;
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u32 out_data;
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u32 set_data;
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u32 clr_data;
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u32 in_data;
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u32 set_rising;
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u32 clr_rising;
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u32 set_falling;
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u32 clr_falling;
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u32 intstat;
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};
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/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
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* with constant parameters; or in outlined code they execute at runtime.
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*
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* You'd access the controller directly when reading or writing more than
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* one gpio value at a time, and to support wired logic where the value
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* being driven by the cpu need not match the value read back.
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*
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* These are NOT part of the cross-platform GPIO interface
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*/
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static inline struct gpio_controller *__iomem
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__gpio_to_controller(unsigned gpio)
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{
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void *__iomem ptr;
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if (gpio < 32 * 1)
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ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
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else if (gpio < 32 * 2)
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ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
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else if (gpio < 32 * 3)
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ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
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else if (gpio < 32 * 4)
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ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88);
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else
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ptr = NULL;
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return ptr;
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}
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static inline u32 __gpio_mask(unsigned gpio)
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{
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return 1 << (gpio % 32);
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}
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/* The get/set/clear functions will inline when called with constant
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* parameters referencing built-in GPIOs, for low-overhead bitbanging.
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*
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* Otherwise, calls with variable parameters or referencing external
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* GPIOs (e.g. on GPIO expander chips) use outlined functions.
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*/
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
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struct gpio_controller *__iomem g;
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u32 mask;
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g = __gpio_to_controller(gpio);
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mask = __gpio_mask(gpio);
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if (value)
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__raw_writel(mask, &g->set_data);
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else
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__raw_writel(mask, &g->clr_data);
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return;
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}
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__gpio_set_value(gpio, value);
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}
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/* Returns zero or nonzero; works for gpios configured as inputs OR
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* as outputs, at least for built-in GPIOs.
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*
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* NOTE: for built-in GPIOs, changes in reported values are synchronized
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* to the GPIO clock. This is easily seen after calling gpio_set_value()
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* and then immediately gpio_get_value(), where the gpio_get_value() will
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* return the old value until the GPIO clock ticks and the new value gets
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* latched.
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*/
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static inline int gpio_get_value(unsigned gpio)
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{
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struct gpio_controller *__iomem g;
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if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
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return __gpio_get_value(gpio);
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g = __gpio_to_controller(gpio);
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return __gpio_mask(gpio) & __raw_readl(&g->in_data);
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}
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static inline int gpio_cansleep(unsigned gpio)
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{
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if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
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return 0;
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else
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return __gpio_cansleep(gpio);
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}
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static inline int gpio_to_irq(unsigned gpio)
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{
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if (gpio >= DAVINCI_N_GPIO)
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return -EINVAL;
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return DAVINCI_N_AINTC_IRQ + gpio;
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}
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static inline int irq_to_gpio(unsigned irq)
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{
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/* caller guarantees gpio_to_irq() succeeded */
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return irq - DAVINCI_N_AINTC_IRQ;
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}
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#endif /* __DAVINCI_GPIO_H */
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