c46acb8e20
Commit 1ea0704e0d
(mm: add a ptep_modify_prot transaction abstraction)
triggered on sh build errors like the following:
<-- snip -->
...
CC arch/sh/mm/pg-sh4.o
cc1: warnings being treated as errors
include2/asm/pgtable.h:139: error: 'ptep_get_and_clear' declared inline after being called
include2/asm/pgtable.h:139: error: previous declaration of 'ptep_get_and_clear' was here
make[2]: *** [arch/sh/mm/pg-sh4.o] Error 1
<-- snip -->
Since there's no good reason for marking these global functions as
"inline" this patch therefore removes the inline's.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/*
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* arch/sh/mm/pg-sh7705.c
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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* Copyright (C) 2004 Alex Song
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/threads.h>
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#include <linux/fs.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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static inline void __flush_purge_virtual_region(void *p1, void *virt, int size)
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{
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unsigned long v;
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unsigned long begin, end;
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unsigned long p1_begin;
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begin = L1_CACHE_ALIGN((unsigned long)virt);
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end = L1_CACHE_ALIGN((unsigned long)virt + size);
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p1_begin = (unsigned long)p1 & ~(L1_CACHE_BYTES - 1);
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/* do this the slow way as we may not have TLB entries
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* for virt yet. */
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for (v = begin; v < end; v += L1_CACHE_BYTES) {
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unsigned long p;
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unsigned long ways, addr;
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p = __pa(p1_begin);
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ways = current_cpu_data.dcache.ways;
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addr = CACHE_OC_ADDRESS_ARRAY;
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do {
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unsigned long data;
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addr |= (v & current_cpu_data.dcache.entry_mask);
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data = ctrl_inl(addr);
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if ((data & CACHE_PHYSADDR_MASK) ==
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(p & CACHE_PHYSADDR_MASK)) {
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data &= ~(SH_CACHE_UPDATED|SH_CACHE_VALID);
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ctrl_outl(data, addr);
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}
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addr += current_cpu_data.dcache.way_incr;
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} while (--ways);
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p1_begin += L1_CACHE_BYTES;
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}
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}
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/*
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* clear_user_page
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* @to: P1 address
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* @address: U0 address to be mapped
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*/
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void clear_user_page(void *to, unsigned long address, struct page *pg)
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{
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struct page *page = virt_to_page(to);
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__set_bit(PG_mapped, &page->flags);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) {
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clear_page(to);
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__flush_wback_region(to, PAGE_SIZE);
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} else {
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__flush_purge_virtual_region(to,
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(void *)(address & 0xfffff000),
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PAGE_SIZE);
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clear_page(to);
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__flush_wback_region(to, PAGE_SIZE);
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}
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}
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/*
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* copy_user_page
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* @to: P1 address
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* @from: P1 address
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* @address: U0 address to be mapped
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*/
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void copy_user_page(void *to, void *from, unsigned long address, struct page *pg)
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{
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struct page *page = virt_to_page(to);
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__set_bit(PG_mapped, &page->flags);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) {
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copy_page(to, from);
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__flush_wback_region(to, PAGE_SIZE);
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} else {
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__flush_purge_virtual_region(to,
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(void *)(address & 0xfffff000),
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PAGE_SIZE);
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copy_page(to, from);
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__flush_wback_region(to, PAGE_SIZE);
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}
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}
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/*
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* For SH7705, we have our own implementation for ptep_get_and_clear
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* Copied from pg-sh4.c
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*/
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pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_t pte = *ptep;
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pte_clear(mm, addr, ptep);
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if (!pte_not_present(pte)) {
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unsigned long pfn = pte_pfn(pte);
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if (pfn_valid(pfn)) {
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struct page *page = pfn_to_page(pfn);
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struct address_space *mapping = page_mapping(page);
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if (!mapping || !mapping_writably_mapped(mapping))
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__clear_bit(PG_mapped, &page->flags);
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}
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}
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return pte;
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}
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