b0d5217cfb
Add support for gpiolib calls. This is based on the gpiolib implementation from plat-s3c64xx tree. Add support for external interrupts for GPIO H banks. Add support for GPIO interrupts for all banks. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
71 lines
2.8 KiB
C
71 lines
2.8 KiB
C
/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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*
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* S5PC1XX - GPIO register definitions
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*/
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#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
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#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
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#include <mach/map.h>
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/* S5PC100 */
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#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO
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#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
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#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
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#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
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#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
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#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
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#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
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#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
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#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
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#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
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#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
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#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
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#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
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#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
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#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
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#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
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#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
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#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
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#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
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#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
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#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
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#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
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#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
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#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
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#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
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#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
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#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
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#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
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#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
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#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
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#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
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#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
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#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
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#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
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#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
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#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00)
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#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68)
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#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80)
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/* PDNEN */
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#define S5PC100_PDNEN_CFG_PDNEN (1 << 1)
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#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
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#define S5PC100_PDNEN_POWERDOWN (1 << 0)
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#define S5PC100_PDNEN_NORMAL (0 << 0)
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/* Common part */
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/* External interrupt base is same at both s5pc100 and s5pc110 */
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#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE)
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#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4))
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#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
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#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4))
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#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
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