55ba99eb21
This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/*
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* include/asm-sh/cpu-sh4/freq.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_FREQ_H
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#define __ASM_CPU_SH4_FREQ_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
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defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7343) || \
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defined(CONFIG_CPU_SUBTYPE_SH7366)
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#define FRQCR 0xa4150000
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#define VCLKCR 0xa4150004
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#define SCLKACR 0xa4150008
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#define SCLKBCR 0xa415000c
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#define IrDACLKCR 0xa4150010
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#define MSTPCR0 0xa4150030
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#define MSTPCR1 0xa4150034
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#define MSTPCR2 0xa4150038
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define FRQCR 0xffc80000
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#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
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#define FRQCR0 0xffc80000
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#define FRQCR1 0xffc80004
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#define FRQMR1 0xffc80014
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#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
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#define FRQCR0 0xffc40000
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#define FRQCR1 0xffc40004
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#define FRQMR1 0xffc40014
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#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
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#define FRQCR 0xffc00014
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#else
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#define FRQCR 0xffc00000
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#define FRQCR_PSTBY 0x0200
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#define FRQCR_PLLEN 0x0400
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#define FRQCR_CKOEN 0x0800
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#endif
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#define MIN_DIVISOR_NR 0
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#define MAX_DIVISOR_NR 3
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#endif /* __ASM_CPU_SH4_FREQ_H */
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