4c24da79e2
Common i/o layer changes: - Collect the irb at the correct subchannel when waiting for the clear interrupt during subchannel cleaning befor reIPL - don't stop at the first interrupt that comes in. - Change "extern __inline__" to "static inline". - Remove unneeded qdio includes. Signed-off-by: Cornelia Huck <cohuck@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
229 lines
3.7 KiB
C
229 lines
3.7 KiB
C
#ifndef S390_CIO_IOASM_H
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#define S390_CIO_IOASM_H
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/*
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* TPI info structure
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*/
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struct tpi_info {
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__u32 reserved1 : 16; /* reserved 0x00000001 */
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__u32 irq : 16; /* aka. subchannel number */
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__u32 intparm; /* interruption parameter */
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__u32 adapter_IO : 1;
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__u32 reserved2 : 1;
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__u32 isc : 3;
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__u32 reserved3 : 12;
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__u32 int_type : 3;
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__u32 reserved4 : 12;
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} __attribute__ ((packed));
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/*
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* Some S390 specific IO instructions as inline
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*/
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static inline int stsch(int irq, volatile struct schib *addr)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" stsch 0(%2)\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000), "a" (addr)
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: "cc", "1" );
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return ccode;
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}
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static inline int msch(int irq, volatile struct schib *addr)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" msch 0(%2)\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000L), "a" (addr)
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: "cc", "1" );
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return ccode;
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}
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static inline int msch_err(int irq, volatile struct schib *addr)
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{
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int ccode;
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__asm__ __volatile__(
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" lhi %0,%3\n"
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" lr 1,%1\n"
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" msch 0(%2)\n"
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"0: ipm %0\n"
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" srl %0,28\n"
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"1:\n"
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#ifdef CONFIG_ARCH_S390X
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".section __ex_table,\"a\"\n"
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" .align 8\n"
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" .quad 0b,1b\n"
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".previous"
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#else
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".section __ex_table,\"a\"\n"
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" .align 4\n"
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" .long 0b,1b\n"
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".previous"
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#endif
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: "=&d" (ccode)
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: "d" (irq | 0x10000L), "a" (addr), "K" (-EIO)
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: "cc", "1" );
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return ccode;
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}
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static inline int tsch(int irq, volatile struct irb *addr)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" tsch 0(%2)\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000L), "a" (addr)
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: "cc", "1" );
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return ccode;
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}
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static inline int tpi( volatile struct tpi_info *addr)
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{
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int ccode;
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__asm__ __volatile__(
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" tpi 0(%1)\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "a" (addr)
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: "cc", "1" );
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return ccode;
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}
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static inline int ssch(int irq, volatile struct orb *addr)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" ssch 0(%2)\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000L), "a" (addr)
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: "cc", "1" );
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return ccode;
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}
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static inline int rsch(int irq)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" rsch\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000L)
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: "cc", "1" );
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return ccode;
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}
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static inline int csch(int irq)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" csch\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000L)
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: "cc", "1" );
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return ccode;
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}
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static inline int hsch(int irq)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" hsch\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000L)
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: "cc", "1" );
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return ccode;
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}
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static inline int xsch(int irq)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" .insn rre,0xb2760000,%1,0\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (irq | 0x10000L)
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: "cc", "1" );
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return ccode;
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}
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static inline int chsc(void *chsc_area)
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{
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int cc;
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__asm__ __volatile__ (
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".insn rre,0xb25f0000,%1,0 \n\t"
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"ipm %0 \n\t"
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"srl %0,28 \n\t"
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: "=d" (cc)
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: "d" (chsc_area)
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: "cc" );
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return cc;
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}
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static inline int iac( void)
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{
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int ccode;
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__asm__ __volatile__(
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" iac 1\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode) : : "cc", "1" );
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return ccode;
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}
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static inline int rchp(int chpid)
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{
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int ccode;
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__asm__ __volatile__(
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" lr 1,%1\n"
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" rchp\n"
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" ipm %0\n"
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" srl %0,28"
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: "=d" (ccode)
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: "d" (chpid)
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: "cc", "1" );
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return ccode;
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}
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#endif
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