998ec2901a
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/*
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* This is a direct copy of the ev96100.h file, with a global
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* search and replace. The numbers are the same.
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*
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* The reason I'm duplicating this is so that the 64120/96100
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* defines won't be confusing in the source code.
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*/
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#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H
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#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H
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/*
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* GT64120 config space base address
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*/
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extern unsigned long gt64120_base;
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#define GT64120_BASE (gt64120_base)
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/*
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* PCI Bus allocation
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*/
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#define GT_PCI_MEM_BASE 0x12000000UL
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#define GT_PCI_MEM_SIZE 0x02000000UL
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#define GT_PCI_IO_BASE 0x10000000UL
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#define GT_PCI_IO_SIZE 0x02000000UL
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#define GT_ISA_IO_BASE PCI_IO_BASE
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/*
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* Duart I/O ports.
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*/
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#define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20)
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#define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00)
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/*
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* EV64120 interrupt controller register base.
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*/
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#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
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/*
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* EV64120 UART register base.
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*/
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#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
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#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
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#define EV64120_BASE_BAUD ( 3686400 / 16 )
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#define EV64120_UART_IRQ 6
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/*
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* PCI interrupts will come in on either the INTA or INTD interrups lines,
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* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
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* boards, they all either come in on IntD or they all come in on IntA, they
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* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
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* "requested" interrupt numbers and go through the list whenever we get an
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* IntA/D.
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*
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* Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
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* INTD is 11.
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*/
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#define GT_TIMER 4
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#define GT_INTA 2
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#define GT_INTD 5
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#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */
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