a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
124 lines
5.6 KiB
C
124 lines
5.6 KiB
C
/*
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* pcic.h: JavaEngine 1 specific PCI definitions.
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*
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* Copyright (C) 1998 V. Roganov and G. Raiko
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*/
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#ifndef __SPARC_PCIC_H
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#define __SPARC_PCIC_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/smp.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <asm/pbm.h>
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struct linux_pcic {
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void __iomem *pcic_regs;
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unsigned long pcic_io;
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void __iomem *pcic_config_space_addr;
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void __iomem *pcic_config_space_data;
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struct resource pcic_res_regs;
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struct resource pcic_res_io;
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struct resource pcic_res_cfg_addr;
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struct resource pcic_res_cfg_data;
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struct linux_pbm_info pbm;
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struct pcic_ca2irq *pcic_imap;
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int pcic_imdim;
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};
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extern int pcic_probe(void);
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/* Erm... MJ redefined pcibios_present() so that it does not work early. */
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extern int pcic_present(void);
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extern void sun4m_pci_init_IRQ(void);
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#endif
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/* Size of PCI I/O space which we relocate. */
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#define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
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/* PCIC Register Set. */
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#define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
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#define PCI_SIZE_0 0x44 /* 32 bits */
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#define PCI_SIZE_1 0x48 /* 32 bits */
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#define PCI_SIZE_2 0x4c /* 32 bits */
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#define PCI_SIZE_3 0x50 /* 32 bits */
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#define PCI_SIZE_4 0x54 /* 32 bits */
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#define PCI_SIZE_5 0x58 /* 32 bits */
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#define PCI_PIO_CONTROL 0x60 /* 8 bits */
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#define PCI_DVMA_CONTROL 0x62 /* 8 bits */
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#define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0)
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#define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0)
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#define PCI_DVMA_CONTROL_IOTLB_DISABLE 0
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#define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4)
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#define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
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#define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
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#define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
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#define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
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#define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
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#define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
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#define PCI_SYS_INT_PENDING_PIO 0x40000000
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#define PCI_SYS_INT_PENDING_DMA 0x20000000
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#define PCI_SYS_INT_PENDING_PCI 0x10000000
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#define PCI_SYS_INT_PENDING_APSR 0x08000000
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#define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
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#define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
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#define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
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#define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
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#define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80
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#define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40
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#define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20
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#define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10
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#define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
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#define PCI_INT_SELECT_LO 0x88 /* 16 bits */
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#define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
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#define PCI_INT_SELECT_HI 0x8c /* 16 bits */
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#define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
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#define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
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#define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
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#define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
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#define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
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#define PCI_SMBAR0 0xa0 /* 8 bits */
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#define PCI_MSIZE0 0xa1 /* 8 bits */
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#define PCI_PMBAR0 0xa2 /* 8 bits */
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#define PCI_SMBAR1 0xa4 /* 8 bits */
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#define PCI_MSIZE1 0xa5 /* 8 bits */
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#define PCI_PMBAR1 0xa6 /* 8 bits */
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#define PCI_SIBAR 0xa8 /* 8 bits */
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#define PCI_SIBAR_ADDRESS_MASK 0xf
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#define PCI_ISIZE 0xa9 /* 8 bits */
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#define PCI_ISIZE_16M 0xf
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#define PCI_ISIZE_32M 0xe
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#define PCI_ISIZE_64M 0xc
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#define PCI_ISIZE_128M 0x8
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#define PCI_ISIZE_256M 0x0
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#define PCI_PIBAR 0xaa /* 8 bits */
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#define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
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#define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
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#define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
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#define PCI_SYS_LIMIT 0xb8 /* 32 bits */
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#define PCI_SYS_COUNTER 0xbc /* 32 bits */
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#define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */
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#define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
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#define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
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#define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
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#define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
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#define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \
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((cpu_irq) & 0xf))
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#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
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#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
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#define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
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#define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
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#define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
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#define PCI_SYS_STATUS 0xd0 /* 8 bits */
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#define PCI_SYS_STATUS_RESET_ENABLE (1<<0)
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#define PCI_SYS_STATUS_RESET (1<<1)
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#define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4)
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#define PCI_SYS_STATUS_PCI_RESET (1<<5)
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#define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6)
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#define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7)
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#endif /* !(__SPARC_PCIC_H) */
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