951d6f6d70
The watchdog code currently hardcodes the base address of the timer its using. To support new SoCs, make it support timers at any address. Use the soc_info structure to do this. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
667 lines
16 KiB
C
667 lines
16 KiB
C
/*
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* TI DaVinci DM355 chip specific setup
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*
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* Author: Kevin Hilman, Deep Root Systems, LLC
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*
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* 2007 (c) Deep Root Systems, LLC. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/spi/spi.h>
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#include <asm/mach/map.h>
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#include <mach/dm355.h>
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#include <mach/clock.h>
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#include <mach/cputype.h>
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#include <mach/edma.h>
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#include <mach/psc.h>
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#include <mach/mux.h>
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#include <mach/irqs.h>
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#include <mach/time.h>
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#include <mach/common.h>
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#include "clock.h"
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#include "mux.h"
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/*
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* Device specific clocks
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*/
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#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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.flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
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};
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static struct pll_data pll2_data = {
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.num = 2,
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.phys_base = DAVINCI_PLL2_BASE,
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.flags = PLL_HAS_PREDIV,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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/* FIXME -- crystal rate is board-specific */
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.rate = DM355_REF_FREQ,
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};
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static struct clk pll1_clk = {
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.name = "pll1",
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.parent = &ref_clk,
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.flags = CLK_PLL,
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.pll_data = &pll1_data,
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};
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static struct clk pll1_aux_clk = {
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.name = "pll1_aux_clk",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclk1 = {
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.name = "pll1_sysclk1",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll1_sysclk2 = {
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.name = "pll1_sysclk2",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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.name = "pll1_sysclk3",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll1_sysclk4 = {
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.name = "pll1_sysclk4",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV4,
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};
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static struct clk pll1_sysclkbp = {
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.name = "pll1_sysclkbp",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk vpss_dac_clk = {
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.name = "vpss_dac",
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.parent = &pll1_sysclk3,
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.lpsc = DM355_LPSC_VPSS_DAC,
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};
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static struct clk vpss_master_clk = {
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.name = "vpss_master",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_VPSSMSTR,
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.flags = CLK_PSC,
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};
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static struct clk vpss_slave_clk = {
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.name = "vpss_slave",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_VPSSSLV,
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};
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static struct clk clkout1_clk = {
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.name = "clkout1",
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.parent = &pll1_aux_clk,
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/* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
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};
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static struct clk clkout2_clk = {
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.name = "clkout2",
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.parent = &pll1_sysclkbp,
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};
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static struct clk pll2_clk = {
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.name = "pll2",
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.parent = &ref_clk,
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.flags = CLK_PLL,
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.pll_data = &pll2_data,
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};
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static struct clk pll2_sysclk1 = {
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.name = "pll2_sysclk1",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll2_sysclkbp = {
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.name = "pll2_sysclkbp",
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.parent = &pll2_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk clkout3_clk = {
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.name = "clkout3",
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.parent = &pll2_sysclkbp,
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/* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
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};
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static struct clk arm_clk = {
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.name = "arm_clk",
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.parent = &pll1_sysclk1,
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.lpsc = DAVINCI_LPSC_ARM,
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.flags = ALWAYS_ENABLED,
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};
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/*
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* NOT LISTED below, and not touched by Linux
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* - in SyncReset state by default
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* .lpsc = DAVINCI_LPSC_TPCC,
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* .lpsc = DAVINCI_LPSC_TPTC0,
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* .lpsc = DAVINCI_LPSC_TPTC1,
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* .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
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* .lpsc = DAVINCI_LPSC_MEMSTICK,
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* - in Enabled state by default
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* .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
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* .lpsc = DAVINCI_LPSC_SCR2, // "bus"
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* .lpsc = DAVINCI_LPSC_SCR3, // "bus"
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* .lpsc = DAVINCI_LPSC_SCR4, // "bus"
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* .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
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* .lpsc = DAVINCI_LPSC_CFG27, // "test"
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* .lpsc = DAVINCI_LPSC_CFG3, // "test"
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* .lpsc = DAVINCI_LPSC_CFG5, // "test"
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*/
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static struct clk mjcp_clk = {
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.name = "mjcp",
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.parent = &pll1_sysclk1,
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.lpsc = DAVINCI_LPSC_IMCOP,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART0,
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};
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static struct clk uart1_clk = {
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.name = "uart1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART1,
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};
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static struct clk uart2_clk = {
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.name = "uart2",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_UART2,
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};
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static struct clk i2c_clk = {
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.name = "i2c",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_I2C,
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};
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static struct clk asp0_clk = {
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.name = "asp0",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_McBSP,
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};
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static struct clk asp1_clk = {
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.name = "asp1",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_McBSP1,
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};
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static struct clk mmcsd0_clk = {
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.name = "mmcsd0",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_MMC_SD,
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};
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static struct clk mmcsd1_clk = {
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.name = "mmcsd1",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_MMC_SD1,
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};
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static struct clk spi0_clk = {
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.name = "spi0",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_SPI,
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};
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static struct clk spi1_clk = {
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.name = "spi1",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_SPI1,
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};
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static struct clk spi2_clk = {
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.name = "spi2",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_SPI2,
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};
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static struct clk gpio_clk = {
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.name = "gpio",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_GPIO,
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};
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static struct clk aemif_clk = {
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.name = "aemif",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_AEMIF,
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};
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static struct clk pwm0_clk = {
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.name = "pwm0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM0,
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};
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static struct clk pwm1_clk = {
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.name = "pwm1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM1,
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};
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static struct clk pwm2_clk = {
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.name = "pwm2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM2,
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};
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static struct clk pwm3_clk = {
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.name = "pwm3",
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.parent = &pll1_aux_clk,
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.lpsc = DM355_LPSC_PWM3,
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};
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static struct clk timer0_clk = {
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.name = "timer0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER0,
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};
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static struct clk timer1_clk = {
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.name = "timer1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER1,
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};
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static struct clk timer2_clk = {
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.name = "timer2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER2,
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.usecount = 1, /* REVISIT: why cant' this be disabled? */
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};
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static struct clk timer3_clk = {
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.name = "timer3",
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.parent = &pll1_aux_clk,
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.lpsc = DM355_LPSC_TIMER3,
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};
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static struct clk rto_clk = {
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.name = "rto",
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.parent = &pll1_aux_clk,
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.lpsc = DM355_LPSC_RTO,
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};
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static struct clk usb_clk = {
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.name = "usb",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_USB,
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};
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static struct davinci_clk dm355_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll1", &pll1_clk),
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CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
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CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
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CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
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CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
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CLK(NULL, "pll1_aux", &pll1_aux_clk),
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CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
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CLK(NULL, "vpss_dac", &vpss_dac_clk),
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CLK(NULL, "vpss_master", &vpss_master_clk),
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CLK(NULL, "vpss_slave", &vpss_slave_clk),
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CLK(NULL, "clkout1", &clkout1_clk),
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CLK(NULL, "clkout2", &clkout2_clk),
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CLK(NULL, "pll2", &pll2_clk),
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CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
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CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
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CLK(NULL, "clkout3", &clkout3_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK(NULL, "mjcp", &mjcp_clk),
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CLK(NULL, "uart0", &uart0_clk),
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CLK(NULL, "uart1", &uart1_clk),
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CLK(NULL, "uart2", &uart2_clk),
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CLK("i2c_davinci.1", NULL, &i2c_clk),
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CLK("soc-audio.0", NULL, &asp0_clk),
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CLK("soc-audio.1", NULL, &asp1_clk),
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CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
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CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
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CLK(NULL, "spi0", &spi0_clk),
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CLK(NULL, "spi1", &spi1_clk),
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CLK(NULL, "spi2", &spi2_clk),
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CLK(NULL, "gpio", &gpio_clk),
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CLK(NULL, "aemif", &aemif_clk),
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CLK(NULL, "pwm0", &pwm0_clk),
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CLK(NULL, "pwm1", &pwm1_clk),
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CLK(NULL, "pwm2", &pwm2_clk),
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CLK(NULL, "pwm3", &pwm3_clk),
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CLK(NULL, "timer0", &timer0_clk),
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CLK(NULL, "timer1", &timer1_clk),
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CLK("watchdog", NULL, &timer2_clk),
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CLK(NULL, "timer3", &timer3_clk),
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CLK(NULL, "rto", &rto_clk),
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CLK(NULL, "usb", &usb_clk),
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CLK(NULL, NULL, NULL),
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};
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/*----------------------------------------------------------------------*/
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static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
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static struct resource dm355_spi0_resources[] = {
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{
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.start = 0x01c66000,
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.end = 0x01c667ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_DM355_SPINT0_1,
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.flags = IORESOURCE_IRQ,
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},
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/* Not yet used, so not included:
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* IORESOURCE_IRQ:
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* - IRQ_DM355_SPINT0_0
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* IORESOURCE_DMA:
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* - DAVINCI_DMA_SPI_SPIX
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* - DAVINCI_DMA_SPI_SPIR
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*/
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};
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static struct platform_device dm355_spi0_device = {
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.name = "spi_davinci",
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.id = 0,
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.dev = {
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.dma_mask = &dm355_spi0_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(dm355_spi0_resources),
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.resource = dm355_spi0_resources,
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};
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void __init dm355_init_spi0(unsigned chipselect_mask,
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struct spi_board_info *info, unsigned len)
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{
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/* for now, assume we need MISO */
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davinci_cfg_reg(DM355_SPI0_SDI);
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/* not all slaves will be wired up */
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if (chipselect_mask & BIT(0))
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davinci_cfg_reg(DM355_SPI0_SDENA0);
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if (chipselect_mask & BIT(1))
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davinci_cfg_reg(DM355_SPI0_SDENA1);
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spi_register_board_info(info, len);
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platform_device_register(&dm355_spi0_device);
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}
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/*----------------------------------------------------------------------*/
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/*
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* Device specific mux setup
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*
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* soc description mux mode mode mux dbg
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* reg offset mask mode
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*/
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static const struct mux_config dm355_pins[] = {
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#ifdef CONFIG_DAVINCI_MUX
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MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
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MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
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MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
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MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
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MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
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MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
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MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
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MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
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MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
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MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
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MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
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MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
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INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
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INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
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INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
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EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
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EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
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EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
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#endif
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};
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static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_DM355_CCDC_VDINT0] = 2,
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[IRQ_DM355_CCDC_VDINT1] = 6,
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[IRQ_DM355_CCDC_VDINT2] = 6,
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[IRQ_DM355_IPIPE_HST] = 6,
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[IRQ_DM355_H3AINT] = 6,
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[IRQ_DM355_IPIPE_SDR] = 6,
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[IRQ_DM355_IPIPEIFINT] = 6,
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[IRQ_DM355_OSDINT] = 7,
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[IRQ_DM355_VENCINT] = 6,
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[IRQ_ASQINT] = 6,
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[IRQ_IMXINT] = 6,
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[IRQ_USBINT] = 4,
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[IRQ_DM355_RTOINT] = 4,
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[IRQ_DM355_UARTINT2] = 7,
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[IRQ_DM355_TINT6] = 7,
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[IRQ_CCINT0] = 5, /* dma */
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[IRQ_CCERRINT] = 5, /* dma */
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[IRQ_TCERRINT0] = 5, /* dma */
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[IRQ_TCERRINT] = 5, /* dma */
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[IRQ_DM355_SPINT2_1] = 7,
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[IRQ_DM355_TINT7] = 4,
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[IRQ_DM355_SDIOINT0] = 7,
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[IRQ_MBXINT] = 7,
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[IRQ_MBRINT] = 7,
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[IRQ_MMCINT] = 7,
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[IRQ_DM355_MMCINT1] = 7,
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[IRQ_DM355_PWMINT3] = 7,
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[IRQ_DDRINT] = 7,
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[IRQ_AEMIFINT] = 7,
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[IRQ_DM355_SDIOINT1] = 4,
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[IRQ_TINT0_TINT12] = 2, /* clockevent */
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[IRQ_TINT0_TINT34] = 2, /* clocksource */
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[IRQ_TINT1_TINT12] = 7, /* DSP timer */
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[IRQ_TINT1_TINT34] = 7, /* system tick */
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[IRQ_PWMINT0] = 7,
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[IRQ_PWMINT1] = 7,
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[IRQ_PWMINT2] = 7,
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[IRQ_I2C] = 3,
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[IRQ_UARTINT0] = 3,
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[IRQ_UARTINT1] = 3,
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[IRQ_DM355_SPINT0_0] = 3,
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[IRQ_DM355_SPINT0_1] = 3,
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[IRQ_DM355_GPIO0] = 3,
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[IRQ_DM355_GPIO1] = 7,
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[IRQ_DM355_GPIO2] = 4,
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[IRQ_DM355_GPIO3] = 4,
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[IRQ_DM355_GPIO4] = 7,
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[IRQ_DM355_GPIO5] = 7,
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[IRQ_DM355_GPIO6] = 7,
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[IRQ_DM355_GPIO7] = 7,
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[IRQ_DM355_GPIO8] = 7,
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[IRQ_DM355_GPIO9] = 7,
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[IRQ_DM355_GPIOBNK0] = 7,
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[IRQ_DM355_GPIOBNK1] = 7,
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[IRQ_DM355_GPIOBNK2] = 7,
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[IRQ_DM355_GPIOBNK3] = 7,
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[IRQ_DM355_GPIOBNK4] = 7,
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[IRQ_DM355_GPIOBNK5] = 7,
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[IRQ_DM355_GPIOBNK6] = 7,
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[IRQ_COMMTX] = 7,
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[IRQ_COMMRX] = 7,
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[IRQ_EMUINT] = 7,
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};
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/*----------------------------------------------------------------------*/
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static const s8 dma_chan_dm355_no_event[] = {
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12, 13, 24, 56, 57,
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58, 59, 60, 61, 62,
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63,
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-1
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};
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static struct edma_soc_info dm355_edma_info = {
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.n_channel = 64,
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.n_region = 4,
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.n_slot = 128,
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.n_tc = 2,
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.noevent = dma_chan_dm355_no_event,
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};
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|
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static struct resource edma_resources[] = {
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{
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.name = "edma_cc",
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.start = 0x01c00000,
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.end = 0x01c00000 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma_tc0",
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.start = 0x01c10000,
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|
.end = 0x01c10000 + SZ_1K - 1,
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|
.flags = IORESOURCE_MEM,
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|
},
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|
{
|
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.name = "edma_tc1",
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.start = 0x01c10400,
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|
.end = 0x01c10400 + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = IRQ_CCINT0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = IRQ_CCERRINT,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
/* not using (or muxing) TC*_ERR */
|
|
};
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|
|
|
static struct platform_device dm355_edma_device = {
|
|
.name = "edma",
|
|
.id = -1,
|
|
.dev.platform_data = &dm355_edma_info,
|
|
.num_resources = ARRAY_SIZE(edma_resources),
|
|
.resource = edma_resources,
|
|
};
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static struct map_desc dm355_io_desc[] = {
|
|
{
|
|
.virtual = IO_VIRT,
|
|
.pfn = __phys_to_pfn(IO_PHYS),
|
|
.length = IO_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
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|
|
|
/* Contents of JTAG ID register used to identify exact cpu type */
|
|
static struct davinci_id dm355_ids[] = {
|
|
{
|
|
.variant = 0x0,
|
|
.part_no = 0xb73b,
|
|
.manufacturer = 0x00f,
|
|
.cpu_id = DAVINCI_CPU_ID_DM355,
|
|
.name = "dm355",
|
|
},
|
|
};
|
|
|
|
static void __iomem *dm355_psc_bases[] = {
|
|
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
|
|
};
|
|
|
|
/*
|
|
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
|
|
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
|
|
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
|
|
* T1_TOP: Timer 1, top : <unused>
|
|
*/
|
|
struct davinci_timer_info dm355_timer_info = {
|
|
.timers = davinci_timer_instance,
|
|
.clockevent_id = T0_BOT,
|
|
.clocksource_id = T0_TOP,
|
|
};
|
|
|
|
static struct davinci_soc_info davinci_soc_info_dm355 = {
|
|
.io_desc = dm355_io_desc,
|
|
.io_desc_num = ARRAY_SIZE(dm355_io_desc),
|
|
.jtag_id_base = IO_ADDRESS(0x01c40028),
|
|
.ids = dm355_ids,
|
|
.ids_num = ARRAY_SIZE(dm355_ids),
|
|
.cpu_clks = dm355_clks,
|
|
.psc_bases = dm355_psc_bases,
|
|
.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
|
|
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
|
|
.pinmux_pins = dm355_pins,
|
|
.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
|
|
.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
|
|
.intc_type = DAVINCI_INTC_TYPE_AINTC,
|
|
.intc_irq_prios = dm355_default_priorities,
|
|
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
|
|
.timer_info = &dm355_timer_info,
|
|
.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
|
|
};
|
|
|
|
void __init dm355_init(void)
|
|
{
|
|
davinci_common_init(&davinci_soc_info_dm355);
|
|
}
|
|
|
|
static int __init dm355_init_devices(void)
|
|
{
|
|
if (!cpu_is_davinci_dm355())
|
|
return 0;
|
|
|
|
davinci_cfg_reg(DM355_INT_EDMA_CC);
|
|
platform_device_register(&dm355_edma_device);
|
|
return 0;
|
|
}
|
|
postcore_initcall(dm355_init_devices);
|