95d313cf1c
Impact: new API Add a helper function that takes two cpumask's, and's them and then returns the apicid of the result. This removes a need in io_apic.c that uses a temporary cpumask to hold (mask & cfg->domain). Signed-off-by: Mike Travis <travis@sgi.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
143 lines
3.3 KiB
C
143 lines
3.3 KiB
C
#ifndef __ASM_NUMAQ_APIC_H
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#define __ASM_NUMAQ_APIC_H
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#include <asm/io.h>
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#include <linux/mmzone.h>
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#include <linux/nodemask.h>
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#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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static inline const cpumask_t *target_cpus(void)
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{
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return &CPU_MASK_ALL;
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}
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#define NO_BALANCE_IRQ (1)
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#define esr_disable (1)
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#define INT_DELIVERY_MODE dest_LowestPrio
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#define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */
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static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return physid_isset(apicid, bitmap);
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}
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static inline unsigned long check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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#define apicid_cluster(apicid) (apicid & 0xF0)
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static inline int apic_id_registered(void)
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{
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return 1;
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}
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static inline void init_apic_ldr(void)
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{
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/* Already done in NUMA-Q firmware */
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}
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static inline void setup_apic_routing(void)
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{
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"NUMA-Q", nr_ioapics);
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}
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/*
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* Skip adding the timer int on secondary nodes, which causes
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* a small but painful rift in the time-space continuum.
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*/
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static inline int multi_timer_check(int apic, int irq)
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{
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return apic != 0 && irq == 0;
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}
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static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
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{
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/* We don't have a good way to do this yet - hack */
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return physids_promote(0xFUL);
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}
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/* Mapping from cpu number to logical apicid */
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extern u8 cpu_2_logical_apicid[];
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static inline int cpu_to_logical_apicid(int cpu)
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{
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if (cpu >= NR_CPUS)
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return BAD_APICID;
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return (int)cpu_2_logical_apicid[cpu];
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}
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/*
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* Supporting over 60 cpus on NUMA-Q requires a locality-dependent
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* cpu to APIC ID relation to properly interact with the intelligent
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* mode of the cluster controller.
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*/
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < 60)
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return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
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else
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return BAD_APICID;
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}
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static inline int apicid_to_node(int logical_apicid)
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{
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return logical_apicid >> 4;
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}
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static inline physid_mask_t apicid_to_cpu_present(int logical_apicid)
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{
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int node = apicid_to_node(logical_apicid);
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int cpu = __ffs(logical_apicid & 0xf);
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return physid_mask_of_physid(cpu + 4*node);
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}
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extern void *xquad_portio;
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static inline void setup_portio_remap(void)
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{
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int num_quads = num_online_nodes();
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if (num_quads <= 1)
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return;
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printk("Remapping cross-quad port I/O for %d quads\n", num_quads);
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xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
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printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
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(u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
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}
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static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return (1);
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}
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static inline void enable_apic_mode(void)
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{
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}
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/*
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* We use physical apicids here, not logical, so just return the default
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* physical broadcast to stop people from breaking us
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*/
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static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask)
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{
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return (int) 0xF;
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}
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static inline unsigned int cpu_mask_to_apicid_and(const cpumask_t *cpumask,
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const cpumask_t *andmask)
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{
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return (int) 0xF;
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}
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/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
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static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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#endif /* __ASM_NUMAQ_APIC_H */
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