e65fb0099f
The context makes it clear already that these are clocks, so there's no need for such a suffix. This patch only changes the clocks actually used in the tree. The remaining clocks are renamed in the subsequent architecture specific patches. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
212 lines
4.9 KiB
C
212 lines
4.9 KiB
C
/*
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* Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Luotao Fu, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "../w1.h"
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#include "../w1_int.h"
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#include "../w1_log.h"
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/* According to the mx27 Datasheet the reset procedure should take up to about
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* 1350us. We set the timeout to 500*100us = 50ms for sure */
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#define MXC_W1_RESET_TIMEOUT 500
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/*
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* MXC W1 Register offsets
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*/
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#define MXC_W1_CONTROL 0x00
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#define MXC_W1_TIME_DIVIDER 0x02
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#define MXC_W1_RESET 0x04
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#define MXC_W1_COMMAND 0x06
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#define MXC_W1_TXRX 0x08
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#define MXC_W1_INTERRUPT 0x0A
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#define MXC_W1_INTERRUPT_EN 0x0C
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struct mxc_w1_device {
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void __iomem *regs;
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unsigned int clkdiv;
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struct clk *clk;
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struct w1_bus_master bus_master;
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};
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/*
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* this is the low level routine to
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* reset the device on the One Wire interface
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* on the hardware
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*/
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static u8 mxc_w1_ds2_reset_bus(void *data)
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{
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u8 reg_val;
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unsigned int timeout_cnt = 0;
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struct mxc_w1_device *dev = data;
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__raw_writeb(0x80, (dev->regs + MXC_W1_CONTROL));
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while (1) {
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reg_val = __raw_readb(dev->regs + MXC_W1_CONTROL);
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if (((reg_val >> 7) & 0x1) == 0 ||
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timeout_cnt > MXC_W1_RESET_TIMEOUT)
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break;
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else
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timeout_cnt++;
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udelay(100);
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}
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return (reg_val >> 7) & 0x1;
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}
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/*
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* this is the low level routine to read/write a bit on the One Wire
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* interface on the hardware. It does write 0 if parameter bit is set
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* to 0, otherwise a write 1/read.
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*/
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static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
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{
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struct mxc_w1_device *mdev = data;
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void __iomem *ctrl_addr = mdev->regs + MXC_W1_CONTROL;
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unsigned int timeout_cnt = 400; /* Takes max. 120us according to
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* datasheet.
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*/
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__raw_writeb((1 << (5 - bit)), ctrl_addr);
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while (timeout_cnt--) {
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if (!((__raw_readb(ctrl_addr) >> (5 - bit)) & 0x1))
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break;
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udelay(1);
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}
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return ((__raw_readb(ctrl_addr)) >> 3) & 0x1;
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}
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static int __init mxc_w1_probe(struct platform_device *pdev)
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{
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struct mxc_w1_device *mdev;
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struct resource *res;
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int err = 0;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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mdev = kzalloc(sizeof(struct mxc_w1_device), GFP_KERNEL);
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if (!mdev)
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return -ENOMEM;
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mdev->clk = clk_get(&pdev->dev, "owire");
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if (!mdev->clk) {
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err = -ENODEV;
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goto failed_clk;
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}
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mdev->clkdiv = (clk_get_rate(mdev->clk) / 1000000) - 1;
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res = request_mem_region(res->start, resource_size(res),
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"mxc_w1");
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if (!res) {
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err = -EBUSY;
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goto failed_req;
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}
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mdev->regs = ioremap(res->start, resource_size(res));
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if (!mdev->regs) {
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printk(KERN_ERR "Cannot map frame buffer registers\n");
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goto failed_ioremap;
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}
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clk_enable(mdev->clk);
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__raw_writeb(mdev->clkdiv, mdev->regs + MXC_W1_TIME_DIVIDER);
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mdev->bus_master.data = mdev;
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mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
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mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
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err = w1_add_master_device(&mdev->bus_master);
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if (err)
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goto failed_add;
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platform_set_drvdata(pdev, mdev);
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return 0;
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failed_add:
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iounmap(mdev->regs);
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failed_ioremap:
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release_mem_region(res->start, resource_size(res));
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failed_req:
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clk_put(mdev->clk);
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failed_clk:
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kfree(mdev);
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return err;
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}
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/*
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* disassociate the w1 device from the driver
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*/
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static int mxc_w1_remove(struct platform_device *pdev)
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{
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struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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w1_remove_master_device(&mdev->bus_master);
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iounmap(mdev->regs);
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release_mem_region(res->start, resource_size(res));
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clk_disable(mdev->clk);
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clk_put(mdev->clk);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver mxc_w1_driver = {
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.driver = {
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.name = "mxc_w1",
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},
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.probe = mxc_w1_probe,
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.remove = mxc_w1_remove,
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};
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static int __init mxc_w1_init(void)
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{
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return platform_driver_register(&mxc_w1_driver);
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}
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static void mxc_w1_exit(void)
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{
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platform_driver_unregister(&mxc_w1_driver);
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}
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module_init(mxc_w1_init);
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module_exit(mxc_w1_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Freescale Semiconductors Inc");
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MODULE_DESCRIPTION("Driver for One-Wire on MXC");
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