378 lines
9.2 KiB
C
378 lines
9.2 KiB
C
/*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
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* Elizabeth Clarke (beth@mips.com)
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* Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/compiler.h>
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#include <asm/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/hardirq.h>
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#include <asm/mmu_context.h>
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#include <asm/smp.h>
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#include <asm/time.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/mips_mt.h>
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#define MIPS_CPU_IPI_RESCHED_IRQ 0
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#define MIPS_CPU_IPI_CALL_IRQ 1
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static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
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#if 0
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static void dump_mtregisters(int vpe, int tc)
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{
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printk("vpe %d tc %d\n", vpe, tc);
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settc(tc);
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printk(" c0 status 0x%lx\n", read_vpe_c0_status());
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printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
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printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0());
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printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus());
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printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart());
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printk(" tcbind 0x%lx\n", read_tc_c0_tcbind());
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printk(" tchalt 0x%lx\n", read_tc_c0_tchalt());
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}
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#endif
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void __init sanitize_tlb_entries(void)
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{
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int i, tlbsiz;
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unsigned long mvpconf0, ncpu;
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if (!cpu_has_mipsmt)
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return;
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/* Enable VPC */
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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back_to_back_c0_hazard();
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/* Disable TLB sharing */
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clear_c0_mvpcontrol(MVPCONTROL_STLB);
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mvpconf0 = read_c0_mvpconf0();
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printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
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(mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
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(mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
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tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
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ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
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if (tlbsiz > 0) {
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/* share them out across the vpe's */
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tlbsiz /= ncpu;
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printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
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for (i = 0; i < ncpu; i++) {
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settc(i);
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if (i == 0)
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write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
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else
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write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
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(tlbsiz << 25));
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}
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}
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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}
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static void ipi_resched_dispatch(void)
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{
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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}
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static void ipi_call_dispatch(void)
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{
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
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}
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static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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{
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smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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static struct irqaction irq_resched = {
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.handler = ipi_resched_interrupt,
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.flags = IRQF_DISABLED|IRQF_PERCPU,
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.name = "IPI_resched"
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};
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static struct irqaction irq_call = {
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.handler = ipi_call_interrupt,
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.flags = IRQF_DISABLED|IRQF_PERCPU,
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.name = "IPI_call"
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};
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static void __init smp_copy_vpe_config(void)
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{
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write_vpe_c0_status(
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(read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
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/* set config to be the same as vpe0, particularly kseg0 coherency alg */
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write_vpe_c0_config( read_c0_config());
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/* make sure there are no software interrupts pending */
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write_vpe_c0_cause(0);
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/* Propagate Config7 */
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write_vpe_c0_config7(read_c0_config7());
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write_vpe_c0_count(read_c0_count());
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}
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static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
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unsigned int ncpu)
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{
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if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
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return ncpu;
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/* Deactivate all but VPE 0 */
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if (tc != 0) {
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unsigned long tmp = read_vpe_c0_vpeconf0();
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tmp &= ~VPECONF0_VPA;
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/* master VPE */
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tmp |= VPECONF0_MVP;
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write_vpe_c0_vpeconf0(tmp);
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/* Record this as available CPU */
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cpu_set(tc, phys_cpu_present_map);
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__cpu_number_map[tc] = ++ncpu;
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__cpu_logical_map[ncpu] = tc;
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}
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/* Disable multi-threading with TC's */
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write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
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if (tc != 0)
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smp_copy_vpe_config();
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return ncpu;
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}
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static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
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{
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unsigned long tmp;
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if (!tc)
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return;
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/* bind a TC to each VPE, May as well put all excess TC's
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on the last VPE */
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if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
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write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
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else {
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write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
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/* and set XTC */
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write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
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}
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tmp = read_tc_c0_tcstatus();
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/* mark not allocated and not dynamically allocatable */
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tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
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tmp |= TCSTATUS_IXMT; /* interrupt exempt */
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write_tc_c0_tcstatus(tmp);
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write_tc_c0_tchalt(TCHALT_H);
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}
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/*
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* Common setup before any secondaries are started
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* Make sure all CPU's are in a sensible state before we boot any of the
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* secondarys
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*/
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void __init plat_smp_setup(void)
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{
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unsigned int mvpconf0, ntc, tc, ncpu = 0;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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cpu_set(0, mt_fpu_cpumask);
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#endif /* CONFIG_MIPS_MT_FPAFF */
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if (!cpu_has_mipsmt)
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return;
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/* disable MT so we can configure */
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dvpe();
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dmt();
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/* Put MVPE's into 'configuration state' */
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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mvpconf0 = read_c0_mvpconf0();
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ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
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/* we'll always have more TC's than VPE's, so loop setting everything
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to a sensible state */
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for (tc = 0; tc <= ntc; tc++) {
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settc(tc);
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smp_tc_init(tc, mvpconf0);
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ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
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}
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/* Release config state */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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/* We'll wait until starting the secondaries before starting MVPE */
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printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
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}
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void __init plat_prepare_cpus(unsigned int max_cpus)
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{
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mips_mt_set_cpuoptions();
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/* set up ipi interrupts */
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if (cpu_has_vint) {
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set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
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set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
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}
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cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
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cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
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setup_irq(cpu_ipi_resched_irq, &irq_resched);
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setup_irq(cpu_ipi_call_irq, &irq_call);
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set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
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set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
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}
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/*
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* Setup the PC, SP, and GP of a secondary processor and start it
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* running!
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* smp_bootstrap is the place to resume from
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* __KSTK_TOS(idle) is apparently the stack pointer
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* (unsigned long)idle->thread_info the gp
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* assumes a 1:1 mapping of TC => VPE
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*/
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void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
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{
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struct thread_info *gp = task_thread_info(idle);
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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settc(cpu);
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/* restart */
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write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
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/* enable the tc this vpe/cpu will be running */
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write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
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write_tc_c0_tchalt(0);
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/* enable the VPE */
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write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
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/* stack pointer */
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write_tc_gpr_sp( __KSTK_TOS(idle));
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/* global pointer */
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write_tc_gpr_gp((unsigned long)gp);
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flush_icache_range((unsigned long)gp,
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(unsigned long)(gp + sizeof(struct thread_info)));
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/* finally out of configuration and into chaos */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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evpe(EVPE_ENABLE);
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}
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void __cpuinit prom_init_secondary(void)
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{
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/* Enable per-cpu interrupts */
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/* This is Malta specific: IPI,performance and timer inetrrupts */
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write_c0_status((read_c0_status() & ~ST0_IM ) |
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(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
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}
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void __cpuinit prom_smp_finish(void)
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{
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write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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cpu_set(smp_processor_id(), mt_fpu_cpumask);
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#endif /* CONFIG_MIPS_MT_FPAFF */
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local_irq_enable();
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}
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void prom_cpus_done(void)
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{
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}
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void core_send_ipi(int cpu, unsigned int action)
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{
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int i;
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unsigned long flags;
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int vpflags;
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local_irq_save(flags);
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vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
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switch (action) {
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case SMP_CALL_FUNCTION:
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i = C_SW1;
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break;
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case SMP_RESCHEDULE_YOURSELF:
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default:
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i = C_SW0;
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break;
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}
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/* 1:1 mapping of vpe and tc... */
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settc(cpu);
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write_vpe_c0_cause(read_vpe_c0_cause() | i);
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evpe(vpflags);
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local_irq_restore(flags);
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}
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