David Gibson 14b3466161 [PATCH] Invert sense of SLB class bit ... Currently, we set the class bit in kernel SLB entries, and clear it on user SLB entries. On POWER5, ERAT entries created in real mode have the class bit clear. So to avoid flushing kernel ERAT entries on each context switch, this patch inverts our usage of the class bit, setting it on user SLB entries and clearing it on kernel SLB entries. Booted on POWER5 and G5. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>		2005-09-06 16:57:46 +10:00
..
fault.c
hash_low.S	[PATCH] Remove nested feature sections	2005-08-30 13:52:12 +10:00
hash_native.c	[PATCH] ppc64: Remove redundant uses of physRpn_to_absRpn	2005-08-29 10:53:36 +10:00
hash_utils.c	[PATCH] ppc64: Remove physbase from the lmb_property struct	2005-08-29 10:53:37 +10:00
hugetlbpage.c	[PATCH] Invert sense of SLB class bit	2005-09-06 16:57:46 +10:00
imalloc.c	[PATCH] Four level pagetables for ppc64	2005-08-29 10:53:31 +10:00
init.c	[PATCH] ppc64: poison initmem	2005-09-06 16:07:53 +10:00
Makefile
mmap.c
numa.c	[PATCH] SPARSEMEM EXTREME	2005-09-05 00:05:38 -07:00
slb_low.S	[PATCH] Fix bug in ppc64 dynamic hugepage support	2005-09-01 10:48:20 -07:00
slb.c	[PATCH] Invert sense of SLB class bit	2005-09-06 16:57:46 +10:00
stab.c	[PATCH] ppc64: dynamically allocate segment tables	2005-07-27 16:25:58 -07:00
tlb.c	[PATCH] Four level pagetables for ppc64	2005-08-29 10:53:31 +10:00