97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/*
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* irq.c: GT64120 Interrupt Controller
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*
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* Copyright (C) 2006, Wind River System Inc.
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* Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/bitops.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/irq_cpu.h>
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#include <asm/gt64120.h>
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause();
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if (pending & STATUSF_IP7)
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do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
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else if (pending & STATUSF_IP6)
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do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */
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else if (pending & STATUSF_IP3)
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do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */
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else
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spurious_interrupt();
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}
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/**
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* Initialize GT64120 Interrupt Controller
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*/
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void gt64120_init_pic(void)
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{
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/* clear CPU Interrupt Cause Registers */
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GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
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GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
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/* Disable all interrupts from GT64120 bridge chip */
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GT_WRITE(GT_INTRMASK_OFS, 0x00);
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GT_WRITE(GT_HINTRMASK_OFS, 0x00);
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GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
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GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
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}
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void __init arch_init_irq(void)
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{
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/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
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mips_cpu_irq_init();
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gt64120_init_pic();
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}
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