97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
36 lines
1.0 KiB
C
36 lines
1.0 KiB
C
/*
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* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef _MIPS_SIMINT_H
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#define _MIPS_SIMINT_H
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#include <irq.h>
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#define SIM_INT_BASE 0
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#define MIPSCPU_INT_MB0 2
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#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
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#define MIPS_CPU_TIMER_IRQ 7
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#define MIPSCPU_INT_CPUCTR 7
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#define MSC01E_INT_BASE 64
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#define MIPSCPU_INT_CPUCTR 7
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#define MSC01E_INT_CPUCTR 11
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#endif
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