8f99a16265
This patch add a new section for MIPS to record the block of the hardirq handling for function graph tracer(print_graph_irq) via adding the __irq_entry annotation to the the entrypoints of the hardirqs(the block with irq_enter()...irq_exit()). Thanks goes to Steven & Frederic Weisbecker for their feedbacks. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Nicholas Mc Guire <der.herr@hofr.at> Cc: zhangfx@lemote.com Cc: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Reviewed-by: Frederic Weisbecker <fweisbec@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/676/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
141 lines
3.6 KiB
C
141 lines
3.6 KiB
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
|
|
* Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
|
|
*/
|
|
#ifndef _ASM_IRQ_H
|
|
#define _ASM_IRQ_H
|
|
|
|
#include <linux/linkage.h>
|
|
#include <linux/smp.h>
|
|
|
|
#include <asm/mipsmtregs.h>
|
|
|
|
#include <irq.h>
|
|
|
|
#ifdef CONFIG_I8259
|
|
static inline int irq_canonicalize(int irq)
|
|
{
|
|
return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
|
|
}
|
|
#else
|
|
#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
|
|
#endif
|
|
|
|
#ifdef CONFIG_MIPS_MT_SMTC
|
|
|
|
struct irqaction;
|
|
|
|
extern unsigned long irq_hwmask[];
|
|
extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
|
|
unsigned long hwmask);
|
|
|
|
static inline void smtc_im_ack_irq(unsigned int irq)
|
|
{
|
|
if (irq_hwmask[irq] & ST0_IM)
|
|
set_c0_status(irq_hwmask[irq] & ST0_IM);
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void smtc_im_ack_irq(unsigned int irq)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_MIPS_MT_SMTC */
|
|
|
|
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
|
|
#include <linux/cpumask.h>
|
|
|
|
extern int plat_set_irq_affinity(unsigned int irq,
|
|
const struct cpumask *affinity);
|
|
extern void smtc_forward_irq(unsigned int irq);
|
|
|
|
/*
|
|
* IRQ affinity hook invoked at the beginning of interrupt dispatch
|
|
* if option is enabled.
|
|
*
|
|
* Up through Linux 2.6.22 (at least) cpumask operations are very
|
|
* inefficient on MIPS. Initial prototypes of SMTC IRQ affinity
|
|
* used a "fast path" per-IRQ-descriptor cache of affinity information
|
|
* to reduce latency. As there is a project afoot to optimize the
|
|
* cpumask implementations, this version is optimistically assuming
|
|
* that cpumask.h macro overhead is reasonable during interrupt dispatch.
|
|
*/
|
|
#define IRQ_AFFINITY_HOOK(irq) \
|
|
do { \
|
|
if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\
|
|
smtc_forward_irq(irq); \
|
|
irq_exit(); \
|
|
return; \
|
|
} \
|
|
} while (0)
|
|
|
|
#else /* Not doing SMTC affinity */
|
|
|
|
#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
|
|
|
|
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
|
|
|
|
#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
|
|
|
|
/*
|
|
* Clear interrupt mask handling "backstop" if irq_hwmask
|
|
* entry so indicates. This implies that the ack() or end()
|
|
* functions will take over re-enabling the low-level mask.
|
|
* Otherwise it will be done on return from exception.
|
|
*/
|
|
#define __DO_IRQ_SMTC_HOOK(irq) \
|
|
do { \
|
|
IRQ_AFFINITY_HOOK(irq); \
|
|
if (irq_hwmask[irq] & 0x0000ff00) \
|
|
write_c0_tccontext(read_c0_tccontext() & \
|
|
~(irq_hwmask[irq] & 0x0000ff00)); \
|
|
} while (0)
|
|
|
|
#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
|
|
do { \
|
|
if (irq_hwmask[irq] & 0x0000ff00) \
|
|
write_c0_tccontext(read_c0_tccontext() & \
|
|
~(irq_hwmask[irq] & 0x0000ff00)); \
|
|
} while (0)
|
|
|
|
#else
|
|
|
|
#define __DO_IRQ_SMTC_HOOK(irq) \
|
|
do { \
|
|
IRQ_AFFINITY_HOOK(irq); \
|
|
} while (0)
|
|
#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
|
|
|
|
#endif
|
|
|
|
extern void do_IRQ(unsigned int irq);
|
|
|
|
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
|
|
|
|
extern void do_IRQ_no_affinity(unsigned int irq);
|
|
|
|
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
|
|
|
|
extern void arch_init_irq(void);
|
|
extern void spurious_interrupt(void);
|
|
|
|
extern int allocate_irqno(void);
|
|
extern void alloc_legacy_irqno(void);
|
|
extern void free_irqno(unsigned int irq);
|
|
|
|
/*
|
|
* Before R2 the timer and performance counter interrupts were both fixed to
|
|
* IE7. Since R2 their number has to be read from the c0_intctl register.
|
|
*/
|
|
#define CP0_LEGACY_COMPARE_IRQ 7
|
|
|
|
extern int cp0_compare_irq;
|
|
extern int cp0_perfcount_irq;
|
|
|
|
#endif /* _ASM_IRQ_H */
|