435f8a605d
This reverts commit e4f0ae0ea6
.
It's not wrong, but it's not right either, and everybody seems to agree
that the right fix is probably to do the ccr3 write after the ccr4 one
(and that we also should clean it up a bit). And after that we need to
really validate that all the bits that we write to ccr4 actually do
work.
The old 2.6.19 code was insane, and basically didn't change ccr4 at all
(even though it certainly looks like it was the *intent* to do so). So
let's revert the change that may fix things, just because it's not what
was actually ever tested when the code was written, even if it _was_ the
intent.
There's a discussion on http://lkml.org/lkml/2007/1/9/63 that was
started by the patch that now gets reverted, and that discussion may
well contain the proper long-term fix.
Suggested-by: Adrian Bunk <bunk@stusta.de>
Acked-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
476 lines
12 KiB
C
476 lines
12 KiB
C
#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/timer.h>
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#include "cpu.h"
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/*
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* Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
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*/
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static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
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{
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unsigned char ccr2, ccr3;
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unsigned long flags;
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/* we test for DEVID by checking whether CCR3 is writable */
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local_irq_save(flags);
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, ccr3 ^ 0x80);
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getCx86(0xc0); /* dummy to change bus */
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if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
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ccr2 = getCx86(CX86_CCR2);
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setCx86(CX86_CCR2, ccr2 ^ 0x04);
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getCx86(0xc0); /* dummy */
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if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
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*dir0 = 0xfd;
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else { /* Cx486S A step */
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setCx86(CX86_CCR2, ccr2);
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*dir0 = 0xfe;
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}
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}
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else {
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setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
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/* read DIR0 and DIR1 CPU registers */
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*dir0 = getCx86(CX86_DIR0);
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*dir1 = getCx86(CX86_DIR1);
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}
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local_irq_restore(flags);
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}
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/*
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* Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
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* order to identify the Cyrix CPU model after we're out of setup.c
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*
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* Actually since bugs.h doesn't even reference this perhaps someone should
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* fix the documentation ???
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*/
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static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
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static char Cx86_model[][9] __cpuinitdata = {
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"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
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"M II ", "Unknown"
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};
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static char Cx486_name[][5] __cpuinitdata = {
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"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
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"SRx2", "DRx2"
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};
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static char Cx486S_name[][4] __cpuinitdata = {
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"S", "S2", "Se", "S2e"
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};
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static char Cx486D_name[][4] __cpuinitdata = {
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"DX", "DX2", "?", "?", "?", "DX4"
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};
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static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
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static char cyrix_model_mult1[] __cpuinitdata = "12??43";
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static char cyrix_model_mult2[] __cpuinitdata = "12233445";
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/*
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* Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
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* BIOSes for compatibility with DOS games. This makes the udelay loop
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* work correctly, and improves performance.
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*
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* FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
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*/
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extern void calibrate_delay(void) __init;
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static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
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{
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unsigned long flags;
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if (Cx86_dir0_msb == 3) {
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unsigned char ccr3, ccr5;
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local_irq_save(flags);
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
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ccr5 = getCx86(CX86_CCR5);
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if (ccr5 & 2)
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setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
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setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
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local_irq_restore(flags);
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if (ccr5 & 2) { /* possible wrong calibration done */
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printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
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calibrate_delay();
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c->loops_per_jiffy = loops_per_jiffy;
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}
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}
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}
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static void __cpuinit set_cx86_reorder(void)
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{
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u8 ccr3;
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printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN<45> */
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/* Load/Store Serialize to mem access disable (=reorder it)<29> */
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setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
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/* set load/store serialize from 1GB to 4GB */
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ccr3 |= 0xe0;
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setCx86(CX86_CCR3, ccr3);
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}
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static void __cpuinit set_cx86_memwb(void)
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{
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u32 cr0;
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printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
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/* CCR2 bit 2: unlock NW bit */
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setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
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/* set 'Not Write-through' */
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cr0 = 0x20000000;
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write_cr0(read_cr0() | cr0);
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/* CCR2 bit 2: lock NW bit and set WT1 */
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setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
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}
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static void __cpuinit set_cx86_inc(void)
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{
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unsigned char ccr3;
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printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN<45> */
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/* PCR1 -- Performance Control */
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/* Incrementor on, whatever that is */
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setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
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/* PCR0 -- Performance Control */
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/* Incrementor Margin 10 */
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setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04);
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setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
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}
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/*
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* Configure later MediaGX and/or Geode processor.
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*/
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static void __cpuinit geode_configure(void)
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{
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unsigned long flags;
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u8 ccr3, ccr4;
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local_irq_save(flags);
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/* Suspend on halt power saving and enable #SUSP pin */
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setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* Enable */
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ccr4 = getCx86(CX86_CCR4);
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ccr4 |= 0x38; /* FPU fast, DTE cache, Mem bypass */
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setCx86(CX86_CCR3, ccr3);
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set_cx86_memwb();
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set_cx86_reorder();
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set_cx86_inc();
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local_irq_restore(flags);
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}
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#ifdef CONFIG_PCI
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static struct pci_device_id __cpuinitdata cyrix_55x0[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510) },
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{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520) },
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{ },
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};
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#endif
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static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
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{
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unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
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char *buf = c->x86_model_id;
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const char *p = NULL;
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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clear_bit(0*32+31, c->x86_capability);
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/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
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if ( test_bit(1*32+24, c->x86_capability) ) {
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clear_bit(1*32+24, c->x86_capability);
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set_bit(X86_FEATURE_CXMMX, c->x86_capability);
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}
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do_cyrix_devid(&dir0, &dir1);
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check_cx686_slop(c);
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Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */
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dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
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/* common case step number/rev -- exceptions handled below */
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c->x86_model = (dir1 >> 4) + 1;
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c->x86_mask = dir1 & 0xf;
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/* Now cook; the original recipe is by Channing Corn, from Cyrix.
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* We do the same thing for each generation: we work out
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* the model, multiplier and stepping. Black magic included,
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* to make the silicon step/rev numbers match the printed ones.
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*/
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switch (dir0_msn) {
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unsigned char tmp;
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case 0: /* Cx486SLC/DLC/SRx/DRx */
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p = Cx486_name[dir0_lsn & 7];
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break;
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case 1: /* Cx486S/DX/DX2/DX4 */
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p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
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: Cx486S_name[dir0_lsn & 3];
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break;
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case 2: /* 5x86 */
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Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
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p = Cx86_cb+2;
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break;
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case 3: /* 6x86/6x86L */
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Cx86_cb[1] = ' ';
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Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
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if (dir1 > 0x21) { /* 686L */
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Cx86_cb[0] = 'L';
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p = Cx86_cb;
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(c->x86_model)++;
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} else /* 686 */
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p = Cx86_cb+1;
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/* Emulate MTRRs using Cyrix's ARRs. */
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set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
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/* 6x86's contain this bug */
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c->coma_bug = 1;
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break;
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case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
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#ifdef CONFIG_PCI
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/* It isn't really a PCI quirk directly, but the cure is the
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same. The MediaGX has deep magic SMM stuff that handles the
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SB emulation. It thows away the fifo on disable_dma() which
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is wrong and ruins the audio.
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Bug2: VSA1 has a wrap bug so that using maximum sized DMA
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causes bad things. According to NatSemi VSA2 has another
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bug to do with 'hlt'. I've not seen any boards using VSA2
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and X doesn't seem to support it either so who cares 8).
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VSA1 we work around however.
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*/
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printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
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isa_dma_bridge_buggy = 2;
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/*
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* The 5510/5520 companion chips have a funky PIT.
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*/
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if (pci_dev_present(cyrix_55x0))
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pit_latch_buggy = 1;
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#endif
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c->x86_cache_size=16; /* Yep 16K integrated cache thats it */
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/* GXm supports extended cpuid levels 'ala' AMD */
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if (c->cpuid_level == 2) {
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/* Enable cxMMX extensions (GX1 Datasheet 54) */
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setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
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/* GXlv/GXm/GX1 */
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if((dir1 >= 0x50 && dir1 <= 0x54) || dir1 >= 0x63)
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geode_configure();
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get_model_name(c); /* get CPU marketing name */
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return;
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}
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else { /* MediaGX */
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Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
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p = Cx86_cb+2;
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c->x86_model = (dir1 & 0x20) ? 1 : 2;
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}
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break;
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case 5: /* 6x86MX/M II */
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if (dir1 > 7)
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{
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dir0_msn++; /* M II */
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/* Enable MMX extensions (App note 108) */
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setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
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}
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else
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{
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c->coma_bug = 1; /* 6x86MX, it has the bug. */
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}
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tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
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Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
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p = Cx86_cb+tmp;
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if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
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(c->x86_model)++;
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/* Emulate MTRRs using Cyrix's ARRs. */
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set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
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break;
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case 0xf: /* Cyrix 486 without DEVID registers */
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switch (dir0_lsn) {
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case 0xd: /* either a 486SLC or DLC w/o DEVID */
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dir0_msn = 0;
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p = Cx486_name[(c->hard_math) ? 1 : 0];
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break;
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case 0xe: /* a 486S A step */
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dir0_msn = 0;
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p = Cx486S_name[0];
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break;
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}
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break;
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default: /* unknown (shouldn't happen, we know everyone ;-) */
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dir0_msn = 7;
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break;
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}
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strcpy(buf, Cx86_model[dir0_msn & 7]);
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if (p) strcat(buf, p);
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return;
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}
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/*
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* Handle National Semiconductor branded processors
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*/
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static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
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{
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/* There may be GX1 processors in the wild that are branded
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* NSC and not Cyrix.
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*
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* This function only handles the GX processor, and kicks every
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* thing else to the Cyrix init function above - that should
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* cover any processors that might have been branded differently
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* after NSC acquired Cyrix.
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*
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* If this breaks your GX1 horribly, please e-mail
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* info-linux@ldcmail.amd.com to tell us.
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*/
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/* Handle the GX (Formally known as the GX2) */
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if (c->x86 == 5 && c->x86_model == 5)
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display_cacheinfo(c);
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else
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init_cyrix(c);
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}
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/*
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* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
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* by the fact that they preserve the flags across the division of 5/2.
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* PII and PPro exhibit this behavior too, but they have cpuid available.
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*/
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/*
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* Perform the Cyrix 5/2 test. A Cyrix won't change
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* the flags, while other 486 chips will.
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*/
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static inline int test_cyrix_52div(void)
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{
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unsigned int test;
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__asm__ __volatile__(
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"sahf\n\t" /* clear flags (%eax = 0x0005) */
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"div %b2\n\t" /* divide 5 by 2 */
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"lahf" /* store flags into %ah */
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: "=a" (test)
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: "0" (5), "q" (2)
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: "cc");
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/* AH is 0x02 on Cyrix after the divide.. */
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return (unsigned char) (test >> 8) == 0x02;
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}
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static void __cpuinit cyrix_identify(struct cpuinfo_x86 * c)
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{
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/* Detect Cyrix with disabled CPUID */
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if ( c->x86 == 4 && test_cyrix_52div() ) {
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unsigned char dir0, dir1;
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strcpy(c->x86_vendor_id, "CyrixInstead");
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c->x86_vendor = X86_VENDOR_CYRIX;
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/* Actually enable cpuid on the older cyrix */
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/* Retrieve CPU revisions */
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do_cyrix_devid(&dir0, &dir1);
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dir0>>=4;
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/* Check it is an affected model */
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if (dir0 == 5 || dir0 == 3)
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{
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unsigned char ccr3, ccr4;
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unsigned long flags;
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printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
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local_irq_save(flags);
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
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ccr4 = getCx86(CX86_CCR4);
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setCx86(CX86_CCR4, ccr4 | 0x80); /* enable cpuid */
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setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
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local_irq_restore(flags);
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}
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}
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}
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static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
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.c_vendor = "Cyrix",
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.c_ident = { "CyrixInstead" },
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.c_init = init_cyrix,
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.c_identify = cyrix_identify,
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};
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int __init cyrix_init_cpu(void)
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{
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cpu_devs[X86_VENDOR_CYRIX] = &cyrix_cpu_dev;
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return 0;
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}
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//early_arch_initcall(cyrix_init_cpu);
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static int __init cyrix_exit_cpu(void)
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{
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cpu_devs[X86_VENDOR_CYRIX] = NULL;
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return 0;
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}
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late_initcall(cyrix_exit_cpu);
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static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
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.c_vendor = "NSC",
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.c_ident = { "Geode by NSC" },
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.c_init = init_nsc,
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};
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||
int __init nsc_init_cpu(void)
|
||
{
|
||
cpu_devs[X86_VENDOR_NSC] = &nsc_cpu_dev;
|
||
return 0;
|
||
}
|
||
|
||
//early_arch_initcall(nsc_init_cpu);
|
||
|
||
static int __init nsc_exit_cpu(void)
|
||
{
|
||
cpu_devs[X86_VENDOR_NSC] = NULL;
|
||
return 0;
|
||
}
|
||
|
||
late_initcall(nsc_exit_cpu);
|