9b53a9e28a
The following features are supported: plane 0 works as a regular frame buffer, can be accessed by /dev/fb0 plane 1 has two AOIs (area of interest), can be accessed by /dev/fb1 and /dev/fb2 plane 2 has two AOIs, can be accessed by /dev/fb3 and /dev/fb4 Special ioctls support AOIs All /dev/fb* can be used as regular frame buffer devices, except hardware change can only be made through /dev/fb0. Changing pixel clock has no effect on other fbs. Limitation of usage of AOIs: AOIs on the same plane can not be horizonally overlapped AOIs have horizonal order, i.e. AOI0 should be always on top of AOI1 AOIs can not beyond phisical display area. Application should check AOI geometry before changing physical resolution on /dev/fb0 required command line parameters to preallocate memory for frame buffer diufb. optional command line parameters to set modes and monitor video=fslfb:[resolution][,bpp][,monitor] Syntax: Resolution xres x yres-bpp@refresh_rate, the -bpp and @refresh_rate are optional eg, 1024x768, 1280x1024, 1280x1024-32, 1280x1024@60, 1280x1024-32@60, 1280x480-32@60 Bpp bpp=32, bpp=24, or bpp=16 Monitor monitor=0, monitor=1, monitor=2 0 is DVI 1 is Single link LVDS 2 is Double link LVDS Note: switching monitor is a board feather, not DIU feather. MPC8610HPCD has three monitor ports to swtich to. MPC5121ADS doesn't have additional monitor port. So switching monirot port for MPC5121ADS has no effect. If compiled as a module, it takes pamameters mode, bpp, monitor with the same syntax above. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: "Antonino A. Daplas" <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
326 lines
7.2 KiB
Plaintext
326 lines
7.2 KiB
Plaintext
/*
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* MPC8610 HPCD Device Tree Source
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*
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* Copyright 2007-2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License Version 2 as published
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* by the Free Software Foundation.
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*/
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/dts-v1/;
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/ {
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model = "MPC8610HPCD";
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compatible = "fsl,MPC8610HPCD";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8610@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>; // L1
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i-cache-size = <32768>; // L1
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; // 512M at 0x0
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};
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board-control@e8000000 {
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compatible = "fsl,fpga-pixis";
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reg = <0xe8000000 32>; // pixis at 0xe8000000
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};
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soc@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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compatible = "fsl,mpc8610-immr", "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x1000>;
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bus-frequency = <0>;
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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cs4270:codec@4f {
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compatible = "cirrus,cs4270";
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reg = <0x4f>;
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/* MCLK source is a stand-alone oscillator */
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clock-frequency = <12288000>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <28 2>;
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interrupt-parent = <&mpic>;
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};
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display@2c000 {
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compatible = "fsl,diu";
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reg = <0x2c000 100>;
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interrupts = <72 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: interrupt-controller@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8610-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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i2s@16000 {
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compatible = "fsl,mpc8610-ssi";
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cell-index = <0>;
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reg = <0x16000 0x100>;
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interrupt-parent = <&mpic>;
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interrupts = <62 2>;
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fsl,mode = "i2s-slave";
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codec-handle = <&cs4270>;
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};
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ssi@16100 {
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compatible = "fsl,mpc8610-ssi";
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cell-index = <1>;
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reg = <0x16100 0x100>;
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interrupt-parent = <&mpic>;
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interrupts = <63 2>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
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cell-index = <0>;
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reg = <0x21300 0x4>; /* DMA general status register */
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ranges = <0x0 0x21100 0x200>;
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dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <0>;
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reg = <0x0 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@1 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <1>;
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reg = <0x80 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@2 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <2>;
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reg = <0x100 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@3 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <3>;
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reg = <0x180 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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dma@c300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
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cell-index = <1>;
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reg = <0xc300 0x4>; /* DMA general status register */
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ranges = <0x0 0xc100 0x200>;
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dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <0>;
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reg = <0x0 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <60 2>;
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};
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dma-channel@1 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <1>;
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reg = <0x80 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <61 2>;
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};
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dma-channel@2 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <2>;
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reg = <0x100 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <62 2>;
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};
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dma-channel@3 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <3>;
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reg = <0x180 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <63 2>;
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};
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};
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};
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pci0: pci@e0008000 {
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cell-index = <0>;
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compatible = "fsl,mpc8610-pci";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008000 0x1000>;
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bus-range = <0 0>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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0x8800 0 0 1 &mpic 4 1
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0x8800 0 0 2 &mpic 5 1
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0x8800 0 0 3 &mpic 6 1
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0x8800 0 0 4 &mpic 7 1
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/* IDSEL 0x12 */
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0x9000 0 0 1 &mpic 5 1
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0x9000 0 0 2 &mpic 6 1
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0x9000 0 0 3 &mpic 7 1
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0x9000 0 0 4 &mpic 4 1
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>;
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};
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pci1: pcie@e000a000 {
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cell-index = <1>;
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe000a000 0x1000>;
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bus-range = <1 3>;
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ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x1b */
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0xd800 0 0 1 &mpic 2 1
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/* IDSEL 0x1c*/
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0xe000 0 0 1 &mpic 1 1
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0xe000 0 0 2 &mpic 1 1
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0xe000 0 0 3 &mpic 1 1
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0xe000 0 0 4 &mpic 1 1
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/* IDSEL 0x1f */
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0xf800 0 0 1 &mpic 3 0
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0xf800 0 0 2 &mpic 0 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0x0 0xa0000000
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0x02000000 0x0 0xa0000000
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0x0 0x10000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00100000>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x02000000 0x0 0xa0000000
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0x02000000 0x0 0xa0000000
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0x0 0x10000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00100000>;
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};
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};
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};
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};
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