9f2ff54d72
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
174 lines
4.6 KiB
C
174 lines
4.6 KiB
C
/*
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* file: include/asm-blackfin/mach-bf537/mem_map.h
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* based on:
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* author:
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*
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* created:
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* description:
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* Memory MAP Common header file for blackfin BF537/6/4 of processors.
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* rev:
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*
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* modified:
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#ifndef _MEM_MAP_537_H_
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#define _MEM_MAP_537_H_
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#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
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#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
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/* Async Memory Banks */
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#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
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#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
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#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
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#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
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#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
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#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
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#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
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#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
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/* Boot ROM Memory */
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#define BOOT_ROM_START 0xEF000000
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/* Level 1 Memory */
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/* Memory Map for ADSP-BF537 processors */
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#ifdef CONFIG_BFIN_ICACHE
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#define BFIN_ICACHESIZE (16*1024)
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#else
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#define BFIN_ICACHESIZE (0*1024)
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#endif
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#ifdef CONFIG_BF537
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#define L1_CODE_START 0xFFA00000
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#define L1_DATA_A_START 0xFF800000
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#define L1_DATA_B_START 0xFF900000
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#define L1_CODE_LENGTH 0xC000
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
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#define BFIN_DCACHESIZE (32*1024)
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#define BFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x8000
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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#endif /*CONFIG_BF537*/
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/* Memory Map for ADSP-BF536 processors */
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#ifdef CONFIG_BF536
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#define L1_CODE_START 0xFFA00000
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#define L1_DATA_A_START 0xFF804000
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#define L1_DATA_B_START 0xFF904000
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#define L1_CODE_LENGTH 0xC000
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x4000
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
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#define BFIN_DCACHESIZE (32*1024)
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#define BFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x4000
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#define L1_DATA_B_LENGTH 0x4000
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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#endif
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/* Memory Map for ADSP-BF534 processors */
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#ifdef CONFIG_BF534
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#define L1_CODE_START 0xFFA00000
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#define L1_DATA_A_START 0xFF800000
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#define L1_DATA_B_START 0xFF900000
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#define L1_CODE_LENGTH 0xC000
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
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#define BFIN_DCACHESIZE (32*1024)
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#define BFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x8000
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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#endif
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/* Scratch Pad Memory */
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#define L1_SCRATCH_START 0xFFB00000
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#define L1_SCRATCH_LENGTH 0x1000
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#endif /* _MEM_MAP_537_H_ */
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