26b7a78c55
This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
/*
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* include/asm-sh/cpu-sh4/cacheflush.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
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#define __ASM_CPU_SH4_CACHEFLUSH_H
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/*
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* Caches are broken on SH-4 (unless we use write-through
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* caching; in which case they're only semi-broken),
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* so we need them.
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*/
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void flush_cache_all(void);
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void flush_cache_mm(struct mm_struct *mm);
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
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unsigned long pfn);
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void flush_dcache_page(struct page *pg);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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void flush_icache_range(unsigned long start, unsigned long end);
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void flush_cache_sigtramp(unsigned long addr);
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void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len);
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#define flush_icache_page(vma,pg) do { } while (0)
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/* Initialization of P3 area for copy_user_page */
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void p3_cache_init(void);
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#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
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