android_kernel_xiaomi_sm8350/arch/blackfin/kernel/vmlinux.lds.S
Sonic Zhang b85b82d980 [Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978

Section data_l1_cacheline_aligned should be defined in
link script of kernel, when L1 data sram bank A is not available.

In bf536 with all data cache is enabled, there is no L1 data sram.
Current link script won't define section data_l1.cacheline_aligned in
this case. But, if user select put cacheline_aligned data into l1 sram
in kernel menuconfig, these data will be dropped and access to these
data will trigger data CPLB exception.

Do panic in l1 relocation code as well.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24 06:13:37 +08:00

238 lines
4.5 KiB
ArmAsm

/*
* File: arch/blackfin/kernel/vmlinux.lds.S
* Based on: none - original work
* Author:
*
* Created: Tue Sep 21 2004
* Description: Master linker script for blackfin architecture
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define VMLINUX_SYMBOL(_sym_) _##_sym_
#include <asm-generic/vmlinux.lds.h>
#include <asm/mem_map.h>
#include <asm/page.h>
#include <asm/thread_info.h>
OUTPUT_FORMAT("elf32-bfin")
ENTRY(__start)
_jiffies = _jiffies_64;
SECTIONS
{
. = CONFIG_BOOT_LOAD;
/* Neither the text, ro_data or bss section need to be aligned
* So pack them back to back
*/
.text :
{
__text = .;
_text = .;
__stext = .;
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT
KPROBES_TEXT
*(.text.*)
*(.fixup)
. = ALIGN(16);
___start___ex_table = .;
*(__ex_table)
___stop___ex_table = .;
__etext = .;
}
/* Just in case the first read only is a 32-bit access */
RO_DATA(4)
.bss :
{
. = ALIGN(4);
___bss_start = .;
*(.bss .bss.*)
*(COMMON)
___bss_stop = .;
}
.data :
{
__sdata = .;
/* This gets done first, so the glob doesn't suck it in */
. = ALIGN(32);
*(.data.cacheline_aligned)
#if !L1_DATA_A_LENGTH
. = ALIGN(32);
*(.data_l1.cacheline_aligned)
#endif
DATA_DATA
*(.data.*)
CONSTRUCTORS
/* make sure the init_task is aligned to the
* kernel thread size so we can locate the kernel
* stack properly and quickly.
*/
. = ALIGN(THREAD_SIZE);
*(.init_task.data)
__edata = .;
}
/* The init section should be last, so when we free it, it goes into
* the general memory pool, and (hopefully) will decrease fragmentation
* a tiny bit. The init section has a _requirement_ that it be
* PAGE_SIZE aligned
*/
. = ALIGN(PAGE_SIZE);
___init_begin = .;
.init.text :
{
. = ALIGN(PAGE_SIZE);
__sinittext = .;
INIT_TEXT
__einittext = .;
}
.init.data :
{
. = ALIGN(16);
INIT_DATA
}
.init.setup :
{
. = ALIGN(16);
___setup_start = .;
*(.init.setup)
___setup_end = .;
}
.initcall.init :
{
___initcall_start = .;
INITCALLS
___initcall_end = .;
}
.con_initcall.init :
{
___con_initcall_start = .;
*(.con_initcall.init)
___con_initcall_end = .;
}
SECURITY_INIT
.init.ramfs :
{
. = ALIGN(4);
___initramfs_start = .;
*(.init.ramfs)
___initramfs_end = .;
}
__l1_lma_start = .;
#if L1_CODE_LENGTH
# define LDS_L1_CODE *(.l1.text)
#else
# define LDS_L1_CODE
#endif
.text_l1 L1_CODE_START : AT(LOADADDR(.init.ramfs) + SIZEOF(.init.ramfs))
{
. = ALIGN(4);
__stext_l1 = .;
LDS_L1_CODE
. = ALIGN(4);
__etext_l1 = .;
}
#if L1_DATA_A_LENGTH
# define LDS_L1_A_DATA *(.l1.data)
# define LDS_L1_A_BSS *(.l1.bss)
# define LDS_L1_A_CACHE *(.data_l1.cacheline_aligned)
#else
# define LDS_L1_A_DATA
# define LDS_L1_A_BSS
# define LDS_L1_A_CACHE
#endif
.data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1))
{
. = ALIGN(4);
__sdata_l1 = .;
LDS_L1_A_DATA
__edata_l1 = .;
. = ALIGN(4);
__sbss_l1 = .;
LDS_L1_A_BSS
. = ALIGN(32);
LDS_L1_A_CACHE
. = ALIGN(4);
__ebss_l1 = .;
}
#if L1_DATA_B_LENGTH
# define LDS_L1_B_DATA *(.l1.data.B)
# define LDS_L1_B_BSS *(.l1.bss.B)
#else
# define LDS_L1_B_DATA
# define LDS_L1_B_BSS
#endif
.data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1))
{
. = ALIGN(4);
__sdata_b_l1 = .;
LDS_L1_B_DATA
__edata_b_l1 = .;
. = ALIGN(4);
__sbss_b_l1 = .;
LDS_L1_B_BSS
. = ALIGN(4);
__ebss_b_l1 = .;
}
/* Force trailing alignment of our init section so that when we
* free our init memory, we don't leave behind a partial page.
*/
. = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
. = ALIGN(PAGE_SIZE);
___init_end = .;
__end =.;
STABS_DEBUG
DWARF_DEBUG
/DISCARD/ :
{
EXIT_TEXT
EXIT_DATA
*(.exitcall.exit)
}
}